[PATCH v3 13/19] drm: msm: mdp5: Add MDP5 configuration for MSM8952

[Muzaffer Kadir via B4 Relay]

From: Muzaffer Kadir <muzafferka...@mainlining.org>

Add the mdp5_cfg_hw entry for MDP5 version v1.12 found on MSM8952.

Signed-off-by: Muzaffer Kadir <muzafferka...@mainlining.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 81 ++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index 7c91fc1915f3..d34c94d6f7e2 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
@@ -744,6 +744,86 @@ static const struct mdp5_cfg_hw msm8x76_config = {
        .max_clk = 360000000,
 };
 
+static const struct mdp5_cfg_hw msm8952_config = {
+       .name = "msm8952",
+       .mdp = {
+               .count = 1,
+               .base = { 0x0 },
+               .caps = MDP_CAP_SMP |
+                       0,
+       },
+       .smp = {
+               .mmb_count = 8,
+               .mmb_size = 8192,
+               .clients = {
+                       [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
+                       [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
+               },
+       },
+       .ctl = {
+               .count = 3,
+               .base = { 0x01000, 0x01200, 0x01400 },
+               .flush_hw_mask = 0xffffffff,
+       },
+       .pipe_vig = {
+               .count = 1,
+               .base = { 0x04000 },
+               .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
+                               MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
+                               MDP_PIPE_CAP_DECIMATION,
+       },
+       .pipe_rgb = {
+               .count = 2,
+               .base = { 0x14000, 0x16000 },
+               .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
+                               MDP_PIPE_CAP_DECIMATION,
+       },
+       .pipe_dma = {
+               .count = 1,
+               .base = { 0x24000 },
+               .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
+       },
+       .pipe_cursor = {
+               .count = 1,
+               .base = { 0x440DC },
+               .caps = MDP_PIPE_CAP_HFLIP      |
+                       MDP_PIPE_CAP_VFLIP      |
+                       MDP_PIPE_CAP_SW_PIX_EXT |
+                       MDP_PIPE_CAP_CURSOR     |
+                       0,
+       },
+       .lm = {
+               .count = 2,
+               .base = { 0x44000, 0x47000 },
+               .instances = {
+                               { .id = 0, .pp = 0, .dspp = 0,
+                                 .caps = MDP_LM_CAP_DISPLAY, },
+                               { .id = 3, .pp = -1, .dspp = -1,
+                                 .caps = MDP_LM_CAP_WB },
+                            },
+               .nb_stages = 8,
+               .max_width = 2048,
+               .max_height = 0xFFFF,
+       },
+       .dspp = {
+               .count = 1,
+               .base = { 0x54000 },
+
+       },
+       .pp = {
+               .count = 3,
+               .base = { 0x70000, 0x70800, 0x72000 },
+       },
+       .intf = {
+               .base = { 0x00000, 0x6a800 },
+               .connect = {
+                       [0] = INTF_DISABLED,
+                       [1] = INTF_DSI,
+               },
+       },
+       .max_clk = 320000000,
+};
+
 static const struct mdp5_cfg_hw msm8x53_config = {
        .name = "msm8x53",
        .mdp = {
@@ -1017,6 +1097,7 @@ static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
        { .revision = 9, .config = { .hw = &msm8x94_config } },
        { .revision = 7, .config = { .hw = &msm8x96_config } },
        { .revision = 11, .config = { .hw = &msm8x76_config } },
+       { .revision = 12, .config = { .hw = &msm8952_config } },
        { .revision = 14, .config = { .hw = &msm8937_config } },
        { .revision = 15, .config = { .hw = &msm8917_config } },
        { .revision = 16, .config = { .hw = &msm8x53_config } },

-- 
2.55.0