The INT2 GDSC on Kaanapali (SM8850) powers a subset of the DPU source pipes (VIG2/VIG3/DMA5). Add it as a second power domain of the display-controller (DPU) node, alongside the existing MMCX performance-state power domain.
The MDSS node's CORE_GDSC is unaffected, since it continues to power the rest of the MDSS hardware on its own. Signed-off-by: Yongxing Mou <[email protected]> --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index ace19b8b12d7..b3e3cd1d311c 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3619,7 +3619,9 @@ mdss_mdp: display-controller@9801000 { operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&dispcc DISP_CC_MDSS_CORE_INT2_GDSC>; + power-domain-names = "mmcx", "int2"; ports { #address-cells = <1>; -- 2.43.0
