Describe the optional power domain for cache controllers.
Signed-off-by: Linus Walleij <[email protected]>
---
Documentation/devicetree/bindings/cache/l2c2x0.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml
b/Documentation/devicetree/bindings/cache/l2c2x0.yaml
index ee604117ffb3..4e568c2a34ef 100644
--- a/Documentation/devicetree/bindings/cache/l2c2x0.yaml
+++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml
@@ -68,6 +68,8 @@ properties:
power-domains:
maxItems: 1
+ description:
+ Power domain controlling the cache controller.
arm,data-latency:
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
--
2.55.0
