From: Francesco Dolcini <[email protected]> Add THine THC63LVD827 DPI to LVDS encoder.
The THC63LVD827 is a simple DPI to LVDS encoder that can be configured with input pins. Link: https://www.thine.co.jp/en/products/detail/THC63LVD827.html Signed-off-by: Francesco Dolcini <[email protected]> --- .../display/bridge/thine,thc63lvd827.yaml | 126 ++++++++++++++++++ MAINTAINERS | 5 + 2 files changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/thine,thc63lvd827.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd827.yaml b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd827.yaml new file mode 100644 index 000000000000..ead50802e11e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd827.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd827.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: THine THC63LVD827 DPI to LVDS encoder + +maintainers: + - Francesco Dolcini <[email protected]> + +description: | + The THC63LVD827 converts a 24-bit parallel RGB interface plus HSYNC, + VSYNC and data-enable to single-link or dual-link LVDS. + + The LVDS output data mapping is configured using the MAP and 6B/8B inputs, + that can be controlled by GPIOs. + + The LVDS output link mode (single/dual) is configured using the MODE input. + + The parallel interface pixel clock sample polarity is configurable with the + R/F input strap option. + +properties: + compatible: + const: thine,thc63lvd827 + + map-gpios: + maxItems: 1 + description: + GPIO connected to the MAP input. A high level selects Mapping Mode 1 + and a low level selects Mapping Mode 2. + + mode-gpios: + maxItems: 1 + description: + GPIO connected to the MODE input. A high level selects single-link + LVDS output and a low level selects dual-link LVDS output. + + b6b8-gpios: + maxItems: 1 + description: + GPIO connected to the 6B/8B input. A high level selects 6-bit (21-bit) + mode and a low level selects 8-bit (27-bit) mode. + + powerdown-gpios: + maxItems: 1 + description: + GPIO connected to the active-low /PDWN input. A high level selects + normal operation and a low level power down the chip. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Parallel RGB input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml + unevaluatedProperties: false + + properties: + pclk-sample: + description: + Sample data on falling (0) or rising (1) edges of the pixel + clock signal. + enum: [ 0, 1 ] + default: 0 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: LVDS output 1st link, used in single- and dual-link mode. + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Optional LVDS output 2nd link, for dual-link mode. + + required: + - port@0 + - port@1 + +required: + - compatible + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + lvds-encoder { + compatible = "thine,thc63lvd827"; + + map-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + mode-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + pclk-sample = <1>; + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&lvds_display_in>; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 6215fcb07770..0b5a25a35367 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8580,6 +8580,11 @@ F: Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml F: drivers/gpu/drm/bridge/synopsys/dw-dp.c F: include/drm/bridge/dw_dp.h +DRM DRIVER FOR THINE THC63LVD827 DPI TO LVDS BRIDGE +M: Francesco Dolcini <[email protected]> +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/thine,thc63lvd827.yaml + DRM DRIVER FOR TI DLPC3433 MIPI DSI TO DMD BRIDGE M: Jagan Teki <[email protected]> S: Maintained -- 2.47.3
