Hi Julien,
On Fri, 2026-08-28 at 14:10 +0200, Julien Stephan wrote:
> According to the datasheet, VID_DOWNSAMPLE_CONFIG is at offset 0x8f0;
> 0x8d0 is the VID_CSC_COEFF_0 register.
>
> Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for
> MT8195/MT8188")
> Signed-off-by: Julien Stephan <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
I've checked in the MT8370, MT8390 (MT8188 variants) and MT8395 (MT8195
variants) datasheets and 0x8f0 offset is indeed the correct one.
So,
Reviewed-by: Louis-Alexis Eyraud <[email protected]>
Regards,
Louis-Alexis
