Introduce helpers to read/write FRL Data Flow Metering registers.
Signed-off-by: Ankit Nautiyal <[email protected]>
---
.../gpu/drm/i915/display/intel_hdmi_frl_dfm.c | 42 +++++++++++++++++++
.../gpu/drm/i915/display/intel_hdmi_frl_dfm.h | 5 +++
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
index 56ade6009983..51a09c05bef3 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
@@ -7,7 +7,12 @@
#include <drm/drm_connector.h>
+#include "intel_de.h"
+#include "intel_display_driver.h"
+#include "intel_display_regs.h"
+#include "intel_display_types.h"
#include "intel_hdmi_frl_dfm.h"
+#include "intel_hdmi_frl_dfm_regs.h"
/* DFM constraints and tolerance values */
#define TB_BORROWED_MAX 400
@@ -702,3 +707,40 @@ bool intel_hdmi_frl_dfm_dsc_requirement_met(struct
intel_hdmi_frl_dfm *frl_dfm)
return true;
}
+
+void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_trans = crtc_state->cpu_transcoder;
+ i915_reg_t reg;
+ u32 val;
+
+ if (!crtc_state->frl.enable)
+ return;
+
+ reg = TRANS_HDMI_FRL_DFMWRCTL(display, cpu_trans);
+ val = TB_ACTUAL_OFFSET(crtc_state->frl.tb_actual);
+ intel_de_rmw(display, reg, TB_ACTUAL_OFFSET_MASK, val);
+
+ reg = TRANS_HDMI_FRL_DFMTHRSH(display, cpu_trans);
+ val = TB_MIN_THESHOLD(crtc_state->frl.tb_threshold_min);
+ intel_de_rmw(display, reg, TB_MIN_THESHOLD_MASK, val);
+}
+
+void intel_hdmi_frl_dfm_read(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_trans = crtc_state->cpu_transcoder;
+ u32 val;
+
+ if (!crtc_state->frl.enable)
+ return;
+
+ val = intel_de_read(display, TRANS_HDMI_FRL_DFMWRCTL(display,
cpu_trans));
+ crtc_state->frl.tb_actual =
+ REG_FIELD_GET(TB_ACTUAL_OFFSET_MASK, val);
+
+ val = intel_de_read(display, TRANS_HDMI_FRL_DFMTHRSH(display,
cpu_trans));
+ crtc_state->frl.tb_threshold_min =
+ REG_FIELD_GET(TB_MIN_THESHOLD_MASK, val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
index 70a66679bdbc..1bfc70067518 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
@@ -7,6 +7,8 @@
#include <linux/types.h>
+struct intel_crtc_state;
+
/* All the input config needed to compute DFM requirements */
struct intel_hdmi_frl_dfm_input_config {
/*
@@ -115,4 +117,7 @@ bool intel_hdmi_frl_dfm_nondsc_requirement_met(struct
intel_hdmi_frl_dfm *frl_df
bool
intel_hdmi_frl_dfm_dsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm);
+void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state);
+void intel_hdmi_frl_dfm_read(struct intel_crtc_state *crtc_state);
+
#endif
--
2.50.1
