Add new struture to store FRL related configurations for a pipe. These members to be calculated during compute config phase, when FRL mode is to be used.
Signed-off-by: Ankit Nautiyal <[email protected]> --- .../drm/i915/display/intel_display_types.h | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ba51de6c4e57..00775ad9019c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1445,6 +1445,32 @@ struct intel_crtc_state { /* to track changes in plane color blocks */ bool plane_color_changed; + + struct { + /* Go for FRL training */ + bool enable; + + /* Enable resource based scheduling */ + bool rsrc_sched_en; + + /* can be either 3 or 4 lanes */ + u8 required_lanes; + + /* required rate - can be 3, 6, 8, 10, 12 Gbps */ + u8 required_rate; + + /* FRL DFM Parameters */ + u32 tb_borrowed, tb_actual, tb_threshold_min, active_char_buf_threshold; + + /* FRL DFM DSC Tribytes */ + u32 hcactive_tb, hctotal_tb; + + /* Clock parameters in KHz */ + u32 div18; + + /* link m/n */ + u32 link_m, link_n; + } frl; }; enum intel_pipe_crc_source { -- 2.50.1
