On 7/22/2026 2:50 AM, Dmitry Baryshkov wrote:
On Mon, Jul 20, 2026 at 06:27:28AM +0000, [email protected] wrote:
[Severity: Medium]
By splitting the link setup from the stream setup here, are we exposing an
incomplete read-modify-write in msm_dp_ctrl_config_ctrl_streams()?
When MST programs the link and stream settings separately,
msm_dp_ctrl_config_ctrl_streams() will be called independently. Looking at
msm_dp_ctrl_config_ctrl_streams():
drivers/gpu/drm/msm/dp/dp_ctrl.c:msm_dp_ctrl_config_ctrl_streams() {
...
config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL);
if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420)
config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */
tbd = msm_dp_link_get_test_bits_depth(ctrl->link,
msm_dp_panel->msm_dp_mode.bpp);
config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
...
}
Since this function reads the register and bitwise-ORs the new values
without clearing the existing stream-specific bitfields (like the BPC or
YUV bits), won't this cause bit accumulation and hardware state corruption
across multiple streams if the link isn't reset in between?
This deserves a comment or a fix.
I'll add a clear-before-programming step for these three fields in the
next revision.
