On 7/6/2026 4:38 PM, Konrad Dybcio wrote: > On 7/6/26 1:07 PM, Konrad Dybcio wrote: >> On 7/5/26 10:14 AM, Akhil P Oommen wrote: >>> From: Abel Vesa <[email protected]> >>> >>> Add the nodes to describe the GPU SMMU. >>> >>> Signed-off-by: Abel Vesa <[email protected]> >>> Signed-off-by: Akhil P Oommen <[email protected]> >>> --- >>> arch/arm64/boot/dts/qcom/eliza.dtsi | 38 >>> +++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 38 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi >>> b/arch/arm64/boot/dts/qcom/eliza.dtsi >>> index c5635f22e2a7..e5b8377e6c3a 100644 >>> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi >>> @@ -2674,6 +2674,44 @@ mdss_dp0_out: endpoint { >>> }; >>> }; >>> >>> + adreno_smmu: iommu@3da0000 { >>> + compatible = "qcom,eliza-smmu-500", "qcom,adreno-smmu", >>> + "qcom,smmu-500", "arm,mmu-500"; >>> + reg = <0x0 0x03da0000 0x0 0x40000>; >>> + #iommu-cells = <2>; >>> + #global-interrupts = <1>; >>> + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, >> >> 674 is the correct globla > > (modulo the issue i explained below) > > [...] > >> This list is not quite correct. It must be sorted by the context index, >> to which a given interrupt corresponds to - the driver relies on that >> to give you information about where a context fault happens >> >> Moreover, I see that the interrupt sheet has the bug where some >> interrupts are offset by 32 from the base vector, and others are offset >> by 31 (i.e. the SPI number doesn't equal irq vector - 32) - please find >> out which mapping is correct with the right folks
I reviewed this and looks correct to me. Also, this matches the downstream configuration. Did you confuse with Dest Port vs Vector ID in the documentation? -Akhil. > > Konrad
