Hi all, Gentle ping for this series, thanks.
On 6/3/2026 11:35 AM, Chaoyi Chen wrote: > From: Chaoyi Chen <[email protected]> > > This series is dedicated to enhancing the DSI controller and PHY timing > interaction, refining the lane rate calculation, and addressing the > associated hardware limitations. > > Changes in v2: > - Link to v1: > https://lore.kernel.org/all/[email protected]/ > - Fix the unit conversion for max_mbps. > - Split the lane rate calculation into a separate patch. > - Add more comment about timing config. > > Chaoyi Chen (3): > drm/rockchip: dsi: Add maximum per lane bit rate calculation > drm/rockchip: dsi: Add dphy_get_timing support for multiple PHY types > drm/rockchip: dsi: Relax the lane rate margin requirements > > .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 66 +++++++++++++++++-- > 1 file changed, 60 insertions(+), 6 deletions(-) > -- Best, Chaoyi
