> -----Original Message----- > From: dri-devel <[email protected]> On Behalf Of > Chaitanya Kumar Borah > Sent: Wednesday, June 17, 2026 2:38 PM > To: [email protected]; [email protected]; intel- > [email protected] > Cc: Samala, Pranay <[email protected]>; Borah, Chaitanya Kumar > <[email protected]> > Subject: [v3 12/14] drm/i915/color: Extract HDR post-CSC LUT programming to > helper function > > From: Pranay Samala <[email protected]> > > Move HDR plane post-CSC LUT programming to improve code organization. > > While at it, remove the segment 0 index register writes as it is not currently > programmed. > > Signed-off-by: Pranay Samala <[email protected]> > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_color.c | 35 ++++++++++++---------- > 1 file changed, 20 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index abf3b3a2e177..360046979556 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -4050,25 +4050,17 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb > *dsb, } > > static void > -xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, > - const struct intel_plane_state *plane_state) > +xelpd_load_hdr_post_csc_lut(struct intel_display *display, > + struct intel_dsb *dsb, > + enum pipe pipe, > + enum plane_id plane, > + const struct drm_color_lut32 *post_csc_lut) > { > - struct intel_display *display = to_intel_display(plane_state); > - const struct drm_plane_state *state = &plane_state->uapi; > - enum pipe pipe = to_intel_plane(state->plane)->pipe; > - enum plane_id plane = to_intel_plane(state->plane)->id; > - const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut- > >data; > int i, lut_size = 32; > u32 lut_val; > > - if (!icl_is_hdr_plane(display, plane)) > - return; > - > intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), > PLANE_PAL_PREC_AUTO_INCREMENT); > - /* TODO: Add macro */ > - intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), > - PLANE_PAL_PREC_AUTO_INCREMENT); > > for (i = 0; i < lut_size + 3; i++) { > if (post_csc_lut) { > @@ -4088,8 +4080,21 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb > *dsb, > } > > intel_de_write_dsb(display, dsb, > PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); > - intel_de_write_dsb(display, dsb, > - PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, > plane, 0), 0); Later we can extend support to include and program this segment as well. For now this looks Good to me. Reviewed-by: Uma Shankar <[email protected]> > +} > + > +static void > +xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, > + const struct intel_plane_state *plane_state) { > + struct intel_display *display = to_intel_display(plane_state); > + const struct drm_plane_state *state = &plane_state->uapi; > + enum pipe pipe = to_intel_plane(state->plane)->pipe; > + enum plane_id plane = to_intel_plane(state->plane)->id; > + const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut > ? > + plane_state->hw.gamma_lut->data : NULL; > + > + if (icl_is_hdr_plane(display, plane)) > + xelpd_load_hdr_post_csc_lut(display, dsb, pipe, plane, > post_csc_lut); > } > > static void > -- > 2.25.1
