Some platforms make an assumption that the i2c controller's
enabled state indicates also the power state of the
controller. This can create a problem when the controller is
in disabled state, because the hardware may assume
incorrectly that it is then also in low-power state.

To fix this, the controller is kept enabled by taking over
the IC_ENABLE register. The controller has to be disabled
when the configuration is updated and when the target
address or the slave address are assigned, so disabling it
when IC_CON, IC_TAR or IC_SAR registers are programmed, and
then re-enabling it again.

Signed-off-by: Heikki Krogerus <[email protected]>
---
 drivers/gpu/drm/xe/xe_i2c.c | 55 +++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_i2c.h |  1 +
 2 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c
index 0495b561957a2..e2d8e77653cf2 100644
--- a/drivers/gpu/drm/xe/xe_i2c.c
+++ b/drivers/gpu/drm/xe/xe_i2c.c
@@ -8,6 +8,7 @@
 #include <drm/drm_print.h>
 #include <linux/array_size.h>
 #include <linux/container_of.h>
+#include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/designware_i2c.h>
 #include <linux/err.h>
@@ -294,11 +295,40 @@ static void xe_i2c_remove_irq(struct xe_i2c *i2c)
        irq_domain_remove(i2c->irqdomain);
 }
 
+/* See "Disabling DW_apb_i2c" in the DesignWare DW_abp_i2c databook. */
+static void xe_i2c_disable(struct xe_i2c *i2c)
+{
+       int timeout = 100;
+       u32 status;
+
+       xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), 1, 0);
+
+       do {
+               status = xe_mmio_read32(i2c->mmio, 
I2C_REG(DW_IC_ENABLE_STATUS));
+               if (!(status & 1))
+                       return;
+               /* Can't sleep here. */
+               udelay(25);
+       } while (timeout--);
+
+       dev_warn(&i2c->adapter->dev, "timeout in disabling adapter\n");
+}
+
 static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val)
 {
        struct xe_i2c *i2c = context;
 
-       *val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET));
+       *val = xe_mmio_read32(i2c->mmio, I2C_REG(reg));
+
+       switch (reg) {
+       case DW_IC_ENABLE:
+       case DW_IC_ENABLE_STATUS:
+               FIELD_MODIFY(DW_IC_ENABLE_ENABLE, val,
+                            i2c->ic_enable & DW_IC_ENABLE_ENABLE);
+               break;
+       default:
+               break;
+       }
 
        return 0;
 }
@@ -307,7 +337,28 @@ static int xe_i2c_write(void *context, unsigned int reg, 
unsigned int val)
 {
        struct xe_i2c *i2c = context;
 
-       xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val);
+       switch (reg) {
+       case DW_IC_CON:
+       case DW_IC_TAR:
+       case DW_IC_SAR:
+               /* Disable the controller. */
+               xe_i2c_disable(i2c);
+
+               /* Write the register. */
+               xe_mmio_write32(i2c->mmio, I2C_REG(reg), val);
+
+               /* Enable the controller. */
+               xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), 0, 1);
+               break;
+       case DW_IC_ENABLE:
+               i2c->ic_enable = val;
+               /* Other fields can be updated except the enable bit. */
+               val |= DW_IC_ENABLE_ENABLE;
+               fallthrough;
+       default:
+               xe_mmio_write32(i2c->mmio, I2C_REG(reg), val);
+               break;
+       }
 
        return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_i2c.h b/drivers/gpu/drm/xe/xe_i2c.h
index b3327db998708..231e36df09017 100644
--- a/drivers/gpu/drm/xe/xe_i2c.h
+++ b/drivers/gpu/drm/xe/xe_i2c.h
@@ -39,6 +39,7 @@ struct xe_i2c {
        struct platform_device *pdev;
        struct i2c_adapter *adapter;
        struct i2c_client *client[XE_I2C_MAX_CLIENTS];
+       unsigned int ic_enable;
 
        struct notifier_block bus_notifier;
        struct work_struct work;
-- 
2.50.1

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