Enable Adaptive Sync SDP for Panel replay + auxless ALPM. First few patches are fixes in existing AS SDP enablement. Later patches add the support to send AS SDP for Panel replay with Link ON and with auxless ALPM (Link-Off).
This series is in continuation from discussions in [1] [2] and more recent [3]: Apart from few patches from [3] new changes include: - Some clean up in drm/dp Macros - Add new DPCD bit to get FAVT PAYLOAD FIELDS PARSING SUPPORT. - Add AS SDP version and PR and VRR specific bits in drm_dp.h. - Modify AS SDP compute config to accomodate PR with Link On and Link Off. - Program Downspread Ctrl DPCD bits. - Make way for T1 and T2 AS SDP transmission timing/position. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ [3] https://lore.kernel.org/intel-gfx/[email protected]/T/#m6e8beab2cc3b6ff9d61f740f107d83a2f4e08114 Rev2: - Drop the redundant version member for AS SDP, and use the member revision - Drop member to store AS SDP transmission time, use simple helper instead. - Use Burst mode to write Panel Replay config DPCDs. - Split AS SDP configuration in compute_config() and compute_config_late() phase. - Always enable AS SDP whenever supported by source + sink. Rev3: - Use ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit also to determine AS SDP v2 support. - Drop patch to make provision to send AS SDP v1. - Add patch to include all relevant AS SDP fields in comparison. - Other refactor improvements suggested by Ville. Rev4: - Add new member coasting vtotal in struct drm_dp_as_sdp and program the coasting vtotal in AS SDP. - Add new helper to get async timing support during PR active. - Correct the patches to write Panel Replay Config DPCDs. - Ensure either PR/VRR have potential to use AS SDP before enabling AS SDP, even though we may not be enabling them at modeset. - Other correction and changes suggested by Ville. Ankit Nautiyal (23): drm/dp: Rename and relocate AS SDP payload field masks drm/dp: Clean up DPRX feature enumeration macros drm/dp: Add bits for AS SDP FAVT Payload Fields Parsing support drm/dp: Add DPCD for configuring AS SDP for PR + VRR drm/dp: Store coasting vtotal in struct drm_dp_as_sdp drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink drm/i915/dp: Account for AS_SDP guardband only when enabled drm/i915/dp: Add a helper to decide if AS SDP can be used drm/i915/dp: Skip AS SDP for DP branch devices drm/i915/dp: Use revision field of AS SDP data structure drm/i915/dp: Include all relevant AS SDP fields in comparison drm/i915/psr: Add helper to get Async Video timing support in PR active drm/i915/dp: Add member to intel_dp to store AS SDP v2 support drm/i915/dp: Allow AS SDP only if v2 is supported drm/i915/psr: Write the PR config DPCDs in burst mode drm/i915/display: Add helper for AS SDP transmission time selection drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off drm/i915/dp: Split AS SDP computation between compute_config and compute_config_late drm/i915/dp: Compute and include coasting vtotal for AS SDP drm/i915/dp: Always enable AS SDP if supported by source + sink drivers/gpu/drm/display/drm_dp_helper.c | 1 + drivers/gpu/drm/i915/display/intel_alpm.c | 20 ++- drivers/gpu/drm/i915/display/intel_display.c | 9 +- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 165 ++++++++++++++---- drivers/gpu/drm/i915/display/intel_dp.h | 2 + .../drm/i915/display/intel_dp_link_training.c | 12 +- .../drm/i915/display/intel_dp_link_training.h | 3 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 37 ++-- drivers/gpu/drm/i915/display/intel_psr.h | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++ include/drm/display/drm_dp.h | 20 ++- include/drm/display/drm_dp_helper.h | 1 + 14 files changed, 226 insertions(+), 58 deletions(-) -- 2.45.2
