Hi All, This patch is now present in drm-fixes, linux-next and linux 7.0-rc3. But it is not present in drm-misc-next. I see it is tagged as drm-misc-fixes-2026-03-05.
I am not sure about the process for merging a patch in drm-fixes to drm-misc-next? Please let me know. Cheers, Biju > -----Original Message----- > From: Biju Das > Sent: 02 March 2026 11:07 > Subject: RE: [PATCH v7] drm: renesas: rz-du: mipi_dsi: Set DSI divider > > Hi, > > > -----Original Message----- > > From: Chris Brandt <[email protected]> > > Sent: 27 February 2026 01:52 > > Subject: [PATCH v7] drm: renesas: rz-du: mipi_dsi: Set DSI divider > > > > Before the MIPI DSI clock source can be configured, the target divide ratio > > needs to be set. > > > > Signed-off-by: Chris Brandt <[email protected]> > > Reviewed-by: Biju Das <[email protected]> > > Tested-by: Biju Das <[email protected]> > > Thanks, applied to drm-misc-fixes after adding fixes tag. > > Cheers, > Biju > > > > --- > > v1->v2: > > - Add spaces around '/' in comments > > - Add target argument in new API > > > > v2->v3: > > - Add missing period in comment (Hugo) > > - Changed '1' to 'PLL5_TARGET_DSI' (Hugo) > > - Added Reviewed-by and Tested-by (Biju) > > > > v3->v4: > > - Fixed up the comments > > - Fixed the match for the divider to set (was missing a * 2) > > > > v4->v5: > > - Rename patch title (Hugo) > > - Add bpp varable for easy reuse (Hugo) > > > > v5->v6: > > - Remove clock diagram that was wrong (Chris) > > > > v6->v7: > > - Rebase to v7.0-rc1 > > --- > > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 16 +++++++++++++++- > > 1 file changed, 15 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_mipi_dsi.c index > > f74a0aa85ba8..29f2b7d24fe5 100644 > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > > @@ -1122,6 +1122,7 @@ static int rzg2l_mipi_dsi_host_attach(struct > > mipi_dsi_host *host, > > struct mipi_dsi_device *device) { > > struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host); > > + int bpp; > > int ret; > > > > if (device->lanes > dsi->num_data_lanes) { @@ -1131,7 +1132,8 @@ > > static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, > > return -EINVAL; > > } > > > > - switch (mipi_dsi_pixel_format_to_bpp(device->format)) { > > + bpp = mipi_dsi_pixel_format_to_bpp(device->format); > > + switch (bpp) { > > case 24: > > break; > > case 18: > > @@ -1162,6 +1164,18 @@ static int rzg2l_mipi_dsi_host_attach(struct > > mipi_dsi_host *host, > > > > drm_bridge_add(&dsi->bridge); > > > > + /* > > + * Report the required division ratio setting for the MIPI clock > > dividers. > > + * > > + * vclk * bpp = hsclk * 8 * num_lanes > > + * > > + * vclk * DSI_AB_divider = hsclk * 16 > > + * > > + * which simplifies to... > > + * DSI_AB_divider = bpp * 2 / num_lanes > > + */ > > + rzg2l_cpg_dsi_div_set_divider(bpp * 2 / dsi->lanes, > > +PLL5_TARGET_DSI); > > + > > return 0; > > } > > > > -- > > 2.52.0
