Hi Geert, > Thanks for your patch!
> What do you mean by "deep sleep"? s2ram? In upstream, s2ram behaves > the same as s2idle, and the LCD works fine after resume from s2ram on > my Amadillo, with and without your patch, > What am I missing? > Thanks! Thank you for your feedback. To clarify the "deep sleep" context, I have tested both s2idle and deep states using: - echo freeze > /sys/power/state - echo mem > /sys/power/state On my hardware, the issue is consistently reproducible in both cases, resulting in a completely white screen after resume. Testing on Stable and Upstream: I have verified this behavior on both the stable and latest upstream kernels. While the patch was originally developed on a stable branch, I have confirmed that it applies cleanly to the current upstream tree and successfully resolves the issue there as well. Context and Environment Difference: I first tested several Armadillo-800 EVA boards more than 10 years ago, and this specific resume failure was already a known, persistent issue back then. After 10 years, I am returning to this platform and testing with my current hardware, and I can confirm the behavior remains exactly the same. Regarding why it works on your side: I cannot be certain about the specific differences in our hardware configurations. However, on my setup, the debug traces clearly confirm that the LDSA1R register is reset to 0 after resume. Video demonstration: I have recorded a short video demonstrating the bug (white screen after pressing "Switch 3" to resume): https://youtu.be/0n9NHeZ7MWU Detailed Logs and Configuration: I have uploaded the kernel config and dmesg logs (including debug traces for LDSA1R) to this Gist: https://gist.github.com/BuiDucPhuc/b31fc7ee784e65d192b2f49a406c3326 Technical Analysis: I focused my debug traces on the LDSA1R register. The logs confirm that during resume, LDSA1R is reset to 0. When the driver updates the registers: 1. It writes the correct address to Side B (Mirror). 2. However, according to Figure 38.13 ("Two-set register switching timing") in the R8A7740 Group Hardware Manual, the transfer from Side B to Side A requires a Frame End interrupt. 3. Since the controller is currently stopped (DO=0), no frame is processed and no Frame End pulse is generated. Consequently, Side A remains 0x00000000, leading to the DMA fetch error and white screen. This priming patch ensures Side A is explicitly initialized while the switching logic is idle, making the driver robust against register context loss. Best regards, Bui Duc Phuc
