Re: [PATCH v4] drm/msm/dp: fix the intf_type of MST interfaces

[Yongxing Mou]

On 11/26/2025 10:50 AM, Yongxing Mou wrote:


On 11/26/2025 8:36 AM, Dmitry Baryshkov wrote:
On Tue, Nov 25, 2025 at 04:22:12PM +0800, Yongxing Mou wrote:
From: Abhinav Kumar <quic_abhin...@quicinc.com>

Interface type of MST interfaces is currently INTF_NONE. Update this to
INTF_DP. And correct the intf_6 intr_underrun/intr_vsync index for
dpu_8_4_sa8775p.

Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
Signed-off-by: Yongxing Mou <yongxing....@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
---
This patch was split out from the MST V3 patch series:
https://lore.kernel.org/all/20250825-msm-dp-mst- 
v3-0-01faacfcd...@oss.qualcomm.com/
---
Changes in v4:
- Splite chagne out from the MST V3 series.

Why?

i just want to spelieete
Sorry, please ignore this message and move to the other reply.>> - Link 
to v3: https://lore.kernel.org/
all/20250825-msm-dp-mst-v3-37-01faacfcd...@oss.qualcomm.com/

Changes in v3:
- Fix through the whole catalog
- Link to v2: https://lore.kernel.org/all/20250609-msm-dp-mst-v2-37- 
a54d8902a...@quicinc.com/

Changes in v2:
- Change the patch order in the series.
- Link to v1: https://lore.kernel.org/all/20241205-dp_mst-v1-3- 
f8618d42a...@quicinc.com/
---
  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h |  6 +++---
  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h  | 12 +++++ 
+------
  drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h |  6 +++---
  3 files changed, 12 insertions(+), 12 deletions(-)

@@ -363,15 +363,15 @@ static const struct dpu_intf_cfg sa8775p_intf[] 
= {
      }, {
          .name = "intf_6", .id = INTF_6,
          .base = 0x3A000, .len = 0x280,
-        .type = INTF_NONE,
+        .type = INTF_DP,
          .controller_id = MSM_DP_CONTROLLER_0,    /* pair with 
intf_0 for DP MST */
          .prog_fetch_lines_worst_case = 24,
-        .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
-        .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
+        .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
+        .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),

This is a separate fix, it should be a separate patch.