On Wed, 15 Oct 2025 at 16:44, Heiko Stübner <[email protected]> wrote: > Am Mittwoch, 3. September 2025, 20:51:00 Mitteleuropäische Sommerzeit schrieb > Cristian Ciocaltea: > > Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed > > value as initially found in vendor driver code supporting the RK3588 > > SoC. As a matter of fact the value matches the rate of the HDMI TX > > reference clock, which is roughly 428.57 MHz. > > > > However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and > > the incorrect register configuration breaks CEC functionality. > > > > Set the timer base according to the actual reference clock rate that > > shall be provided by the platform driver. Otherwise fallback to the > > vendor default. > > > > While at it, also drop the unnecessary empty lines in > > dw_hdmi_qp_init_hw(). > > > > Signed-off-by: Cristian Ciocaltea <[email protected]> > > Reviewed-by: Heiko Stuebner <[email protected]> > > This _does_ look ok to me, but as that touches the main bridge, could > we get a 2nd set of eyes?
Sure can. Reviewed-by: Daniel Stone <[email protected]> Cheers, Daniel
