Hi Tomi, > -----Original Message----- > From: Tomi Valkeinen <tomi.valkeinen+rene...@ideasonboard.com> > Sent: 11 September 2025 15:26 > Subject: Re: [PATCH v8 2/6] clk: renesas: rzv2h-cpg: Add support for DSI > clocks > > Hi, > > On 11/09/2025 11:14, Lad, Prabhakar wrote: > > Hi Tomi, > > > > On Wed, Sep 10, 2025 at 1:30 PM Tomi Valkeinen > > <tomi.valkeinen+rene...@ideasonboard.com> wrote: > >> > >> Hi, > >> > >> On 03/09/2025 19:17, Prabhakar wrote: > >>> From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> > >>> > >>> Add support for PLLDSI and PLLDSI divider clocks. > >>> > >>> Introduce the `renesas-rzv2h-cpg-pll.h` header to centralize and > >>> share PLLDSI related data structures, limits, and algorithms between > >>> the > >>> RZ/V2H(P) CPG and DSI drivers. > >>> > >>> The DSI PLL is functionally similar to the CPG's PLLDSI, but has > >>> slightly different parameter limits and omits the programmable > >>> divider present in CPG. To ensure precise frequency calculations, > >>> especially for milliHz-level accuracy needed by the DSI driver, the > >>> shared algorithm allows both drivers to compute PLL parameters > >>> consistently using the same logic and input clock. > >> > >> Can you elaborate a bit more why a new clock APIs are needed for the > >> DSI PLL? This is the first time I have heard a DSI TX (well, any IP) > >> require more precision than Hz. Is that really the case? Are there other > >> reasons? > >> > > Im pasting the same reply from Fab > > (https://lore.kernel.org/all/TYCPR01MB12093A7D99392BC3D6B5E5864C2BC2@T > > YCPR01MB12093.jpnprd01.prod.outlook.com/#t) > > for the similar concern. > > > > The PLL found inside the DSI IP is very similar to the PLLDSI found in > > the CPG IP block, although the limits for some of the parameters are > > Thanks. As discussed on chat, this confused me: There's a PLLDSI on CPG, > which doesn't provide a DSI > clock, but a pixel clock. And then there's a PLL in the DSI D-PHY which > provides the DSI clock. > > A few comments overall some for this driver but also the dsi driver: > > This hardcodes the refclk rate to 24 MHz with RZ_V2H_OSC_CLK_IN_MEGA in the > header file. That doesn't > feel right, shouldn't the refclk rate come from the clock framework with > clk_get_rate()? > > While not v2h related, I think it would be good to have a comment in the dsi > driver about how the g2l > hs clock rate is derived directly from the pixel clock.
Now the patch [1] has this info [1] https://lore.kernel.org/all/20250912142056.2123725-3-chris.bra...@renesas.com/ Cheers, Biju
