On Thu, Sep 11, 2025 at 10:55:04PM +0800, Xiangxu Yin wrote:
> Introduce DisplayPort PHY configuration routines for QCS615, including
> aux channel setup, lane control, voltage swing tuning, clock config and
> calibration. These callbacks are registered via qmp_phy_cfg to enable DP
> mode on USB/DP switchable Type-C PHYs.
>
> Add register define for QMP_DP_PHY_V2 series.
>
> Signed-off-by: Xiangxu Yin <xiangxu....@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h | 21 +++
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 251
> ++++++++++++++++++++++++++
> 2 files changed, 272 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h
> b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..8b9572d3cdebb70a0f3811f129a40aa78e184638
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2017, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef QCOM_PHY_QMP_DP_PHY_V2_H_
> +#define QCOM_PHY_QMP_DP_PHY_V2_H_
> +
> +// /* Only for QMP V2 PHY - DP PHY registers */
> +#define QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK 0x048
> +#define QSERDES_V2_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
> +#define QSERDES_V2_DP_PHY_AUX_BIST_CFG 0x050
> +
> +#define QSERDES_V2_DP_PHY_VCO_DIV 0x068
> +#define QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL 0x06c
> +#define QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL 0x088
> +
> +#define QSERDES_V2_DP_PHY_SPARE0 0x0ac
> +#define QSERDES_V2_DP_PHY_STATUS 0x0c0
> +
> +#endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> index
> 663024b8c09124f2991b8e0537a9feb60baaa686..7b2b47320cbb2d16e4f316b0f52fdc1bd09fe656
> 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> @@ -28,6 +28,9 @@
> #include "phy-qcom-qmp.h"
> #include "phy-qcom-qmp-pcs-misc-v3.h"
>
> +#include "phy-qcom-qmp-dp-phy.h"
> +#include "phy-qcom-qmp-dp-phy-v2.h"
> +
> #define PHY_INIT_COMPLETE_TIMEOUT 10000
>
> /* set of registers with offsets different per-PHY */
> @@ -619,6 +622,11 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg = {
> .regs = qmp_v3_usb3phy_regs_layout_qcm2290,
> };
>
> +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp);
> +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp);
> +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp);
> +static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp);
> +
> static const struct qmp_phy_cfg qcs615_usb3phy_cfg = {
> .offsets = &qmp_usbc_offsets_v3_qcm2290,
>
> @@ -666,6 +674,11 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = {
> .swing_tbl = &qmp_dp_voltage_swing_hbr2_rbr,
> .pre_emphasis_tbl = &qmp_dp_pre_emphasis_hbr2_rbr,
>
> + .dp_aux_init = qcs615_qmp_dp_aux_init,
> + .configure_dp_tx = qcs615_qmp_configure_dp_tx,
> + .configure_dp_phy = qcs615_qmp_configure_dp_phy,
> + .calibrate_dp_phy = qcs615_qmp_calibrate_dp_phy,
> +
> .reset_list = usb3dpphy_reset_l,
> .num_resets = ARRAY_SIZE(usb3dpphy_reset_l),
> .vreg_list = qmp_phy_qcs615_vreg_l,
> @@ -736,6 +749,244 @@ static int qmp_usbc_com_exit(struct phy *phy)
> return 0;
> }
>
> +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp)
Please rename the functions according to their intention. Are they
common to all USBC PHYs, are they specific to v2 (or v3) PHYs or are
they specific to QCS615? At least this is the approach that has been
used inside combo and eDP PHY drivers.
> +{
> + writel(DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN,
> + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN,
> + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
> +
> + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
> + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
> + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
> + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
> + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
> + writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
> + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
> + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
> + writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
> + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
> + qmp->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qmp->dp_dp_phy + QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static int qcs615_qmp_configure_dp_swing(struct qmp_usbc *qmp)
> +{
> + const struct qmp_phy_cfg *cfg = qmp->cfg;
> + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
> + void __iomem *tx = qmp->dp_tx;
> + void __iomem *tx2 = qmp->dp_tx2;
> + unsigned int v_level = 0, p_level = 0;
> + u8 voltage_swing_cfg, pre_emphasis_cfg;
> + int i;
> +
> + if (dp_opts->lanes > 4) {
> + dev_err(qmp->dev, "Invalid lane_num(%d)\n", dp_opts->lanes);
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < dp_opts->lanes; i++) {
> + v_level = max(v_level, dp_opts->voltage[i]);
> + p_level = max(p_level, dp_opts->pre[i]);
> + }
> +
> + if (v_level > 4 || p_level > 4) {
> + dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n",
> + v_level, p_level);
> + return -EINVAL;
> + }
> +
> + voltage_swing_cfg = (*cfg->swing_tbl)[v_level][p_level];
> + pre_emphasis_cfg = (*cfg->pre_emphasis_tbl)[v_level][p_level];
> +
> + voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
> + pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
> +
> + if (voltage_swing_cfg == 0xff && pre_emphasis_cfg == 0xff)
> + return -EINVAL;
> +
> + writel(voltage_swing_cfg, tx + QSERDES_V3_TX_TX_DRV_LVL);
> + writel(pre_emphasis_cfg, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL);
> + writel(voltage_swing_cfg, tx2 + QSERDES_V3_TX_TX_DRV_LVL);
> + writel(pre_emphasis_cfg, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL);
If QCS615 is a V2 PHY, why are you using V3 registers here?
> +
> + return 0;
> +}
> +
> +static void qmp_usbc_configure_dp_mode(struct qmp_usbc *qmp)
> +{
> + bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
> + u32 val;
> +
> + val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN |
> DP_PHY_PD_CTL_LANE_2_3_PWRDN;
> +
> + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
> +
> + if (reverse)
> + writel(0xc9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
> + else
> + writel(0xd9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
> +}
> +
> +static int qmp_usbc_configure_dp_clocks(struct qmp_usbc *qmp)
> +{
> + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
> + u32 phy_vco_div;
> + unsigned long pixel_freq;
> +
> + switch (dp_opts->link_rate) {
> + case 1620:
> + phy_vco_div = 0x1;
> + pixel_freq = 1620000000UL / 2;
> + break;
> + case 2700:
> + phy_vco_div = 0x1;
> + pixel_freq = 2700000000UL / 2;
> + break;
> + case 5400:
> + phy_vco_div = 0x2;
> + pixel_freq = 5400000000UL / 4;
> + break;
> + default:
> + dev_err(qmp->dev, "link rate:%d not supported\n",
> dp_opts->link_rate);
> + return -EINVAL;
> + }
> + writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_VCO_DIV);
> +
> + clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
> + clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
> +
> + return 0;
> +}
> +
> +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp)
> +{
> + void __iomem *tx = qmp->dp_tx;
> + void __iomem *tx2 = qmp->dp_tx2;
> +
> + /* program default setting first */
> + writel(0x2a, tx + QSERDES_V3_TX_TX_DRV_LVL);
> + writel(0x20, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL);
> + writel(0x2a, tx2 + QSERDES_V3_TX_TX_DRV_LVL);
> + writel(0x20, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL);
Same question here.
> +
> + qcs615_qmp_configure_dp_swing(qmp);
> +}
> +
> +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp)
> +{
> + u32 status;
> + int ret;
> +
> + qmp_usbc_configure_dp_mode(qmp);
> +
> + writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL);
> +
> + ret = qmp_usbc_configure_dp_clocks(qmp);
> + if (ret)
> + return ret;
> +
> + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
> + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
> + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
> + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
> +
> + writel(0x20, qmp->dp_serdes + QSERDES_COM_RESETSM_CNTRL);
> +
> + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_C_READY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000)) {
> + dev_err(qmp->dev, "C_READY not ready\n");
> + return -ETIMEDOUT;
> + }
> +
> + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000)){
> + dev_err(qmp->dev, "FREQ_DONE not ready\n");
> + return -ETIMEDOUT;
> + }
> +
> + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000)){
> + dev_err(qmp->dev, "PLL_LOCKED not ready\n");
> + return -ETIMEDOUT;
> + }
> +
> + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS,
> + status,
> + ((status & BIT(0)) > 0),
> + 500,
> + 10000)){
> + dev_err(qmp->dev, "TSYNC_DONE not ready\n");
> + return -ETIMEDOUT;
> + }
> +
> + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000)){
> + dev_err(qmp->dev, "PHY_READY not ready\n");
> + return -ETIMEDOUT;
> + }
> +
> + writel(0x3f, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> + writel(0x10, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(0x0a, qmp->dp_tx + QSERDES_V3_TX_TX_POL_INV);
> + writel(0x3f, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
> + writel(0x10, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
> + writel(0x0a, qmp->dp_tx2 + QSERDES_V3_TX_TX_POL_INV);
And here
> +
> + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
> + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
> +
> + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS,
> + status,
> + ((status & BIT(1)) > 0),
> + 500,
> + 10000)){
> + dev_err(qmp->dev, "PHY_READY not ready\n");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp)
> +{
> + static const u8 cfg1_settings[] = {0x13, 0x23, 0x1d};
Are these the actual values or is it a C&P from the combo PHY?
> + u8 val;
> +
> + qmp->dp_aux_cfg++;
> + qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> + val = cfg1_settings[qmp->dp_aux_cfg];
> +
> + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
> +
> + return 0;
> +}
> +
> static int qmp_usbc_usb_power_on(struct phy *phy)
> {
> struct qmp_usbc *qmp = phy_get_drvdata(phy);
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
