On Wed, Sep 03, 2025 at 03:41:45PM +0200, Konrad Dybcio wrote:
> On 9/3/25 1:58 PM, Dmitry Baryshkov wrote:
> > From: Jessica Zhang <jessica.zh...@oss.qualcomm.com>
> >
> > Update Qualcomm DT files in order to declare extra stream pixel clocks
> > and extra register resources used on these platforms to support
> > DisplayPort MST.
> >
> > The driver will continue to work with the old DTS files as even after
> > adding MST support the driver will have to support old DTS files which
> > didn't have MST clocks.
> >
> > Signed-off-by: Jessica Zhang <jessica.zh...@oss.qualcomm.com>
> > Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
> > ---
>
> [...]
>
> > diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> > b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> > index
> > 70c87c79e1325f4ab4c81f34e99c0b52be4b3810..e6a7248040095077d6f98d632f4e8a1868432445
> > 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> > @@ -3241,16 +3241,20 @@ mdss_dp0: displayport-controller@ae90000 {
> > <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> > <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> > <&dispcc
> > DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> > - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> > + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
> > + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
> > clock-names = "core_iface",
> > "core_aux",
> > "ctrl_link",
> > "ctrl_link_iface",
> > - "stream_pixel";
> > + "stream_pixel",
> > + "stream_1_pixel";
> >
> > assigned-clocks = <&dispcc
> > DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> > - <&dispcc
> > DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> > + <&dispcc
> > DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
> > + <&dispcc
> > DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
> > assigned-clock-parents = <&usb_prim_qmpphy
> > QMP_USB43DP_DP_LINK_CLK>,
> > + <&usb_prim_qmpphy
> > QMP_USB43DP_DP_VCO_DIV_CLK>,
> > <&usb_prim_qmpphy
> > QMP_USB43DP_DP_VCO_DIV_CLK>;
> >
> > phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
> > @@ -3319,16 +3323,20 @@ mdss_dp1: displayport-controller@ae98000 {
> > <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
> > <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
> > <&dispcc
> > DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
> > - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
> > + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
> > + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
> > clock-names = "core_iface",
> > "core_aux",
> > "ctrl_link",
> > "ctrl_link_iface",
> > - "stream_pixel";
> > + "stream_pixel",
> > + "stream_1_pixel";
> >
> > assigned-clocks = <&dispcc
> > DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
> > - <&dispcc
> > DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
> > + <&dispcc
> > DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
> > + <&dispcc
> > DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
> > assigned-clock-parents = <&usb_sec_qmpphy
> > QMP_USB43DP_DP_LINK_CLK>,
> > + <&usb_sec_qmpphy
> > QMP_USB43DP_DP_VCO_DIV_CLK>,
> > <&usb_sec_qmpphy
> > QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> Something's not right here
No, it's correct as far as I understand. On this platform INTF3 / PIXEL1
is shared between INTF0 / PIXEL and INTF4 / PIXEL2. So it is
counterintuitive, but seems to be correct.
--
With best wishes
Dmitry
