On Tuesday, August 19, 2025 9:16 PM Svyatoslav Ryhel wrote:
> Tegra30 has CSI PAD bits in both PLLD and PLLD2 clocks, that are required
> for correct work of CSI block.
'pad' is just an english word, so please write it in lowercase. Same applies
to the previous patch.
>
> Signed-off-by: Svyatoslav Ryhel <clamo...@gmail.com>
> ---
> drivers/clk/tegra/clk-tegra30.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra30.c
> b/drivers/clk/tegra/clk-tegra30.c index 70e85e2949e0..f033eb1ac26a 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -153,6 +153,7 @@ static unsigned long input_freq;
>
> static DEFINE_SPINLOCK(cml_lock);
> static DEFINE_SPINLOCK(pll_d_lock);
> +static DEFINE_SPINLOCK(pll_d2_lock);
>
> #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
> _clk_num, _gate_flags, _clk_id) \
> @@ -859,7 +860,7 @@ static void __init tegra30_pll_init(void)
>
> /* PLLD2 */
> clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base,
0,
> - &pll_d2_params, NULL);
> + &pll_d2_params, &pll_d2_lock);
Please mention adding this lock in the commit message.
> clks[TEGRA30_CLK_PLL_D2] = clk;
>
> /* PLLD2_OUT0 */
> @@ -1008,6 +1009,18 @@ static void __init tegra30_periph_clk_init(void)
> 0, 48, periph_clk_enb_refcnt);
> clks[TEGRA30_CLK_DSIA] = clk;
>
> + /* csia_pad */
> + clk = clk_register_gate(NULL, "csia_pad", "pll_d",
CLK_SET_RATE_PARENT,
> + clk_base + PLLD_BASE, 26, 0, &pll_d_lock);
> + clk_register_clkdev(clk, "csia_pad", NULL);
> + clks[TEGRA30_CLK_CSIA_PAD] = clk;
> +
> + /* csib_pad */
> + clk = clk_register_gate(NULL, "csib_pad", "pll_d2",
CLK_SET_RATE_PARENT,
> + clk_base + PLLD2_BASE, 26, 0,
&pll_d2_lock);
> + clk_register_clkdev(clk, "csib_pad", NULL);
> + clks[TEGRA30_CLK_CSIB_PAD] = clk;
> +
> /* pcie */
> clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
> 70, periph_clk_enb_refcnt);
