On Mon, Aug 25, 2025 at 10:16:03PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar <quic_abhin...@quicinc.com>
> 
> Whenever virtual channel slot allocation changes, the DP
> source must send the action control trigger sequence to notify
> the sink about the same. This would be applicable during the
> start and stop of the pixel stream. Add the infrastructure
> to be able to send ACT packets for the DP controller when
> operating in MST mode.
> 
> Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
> Signed-off-by: Yongxing Mou <yongxing....@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/dp/dp_ctrl.c    | 39 
> +++++++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/msm/dp/dp_ctrl.h    |  4 ++--
>  drivers/gpu/drm/msm/dp/dp_display.c |  3 ++-
>  drivers/gpu/drm/msm/dp/dp_display.h |  1 +
>  drivers/gpu/drm/msm/dp/dp_reg.h     |  2 ++
>  5 files changed, 44 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c 
> b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index 
> 608a1a077301b2ef3c77c271d873bb4364abe779..16e5ed58e791971d5dca3077cbb77bfcc186505a
>  100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -142,6 +142,7 @@ struct msm_dp_ctrl_private {
>       bool core_clks_on;
>       bool link_clks_on;
>       bool stream_clks_on[DP_STREAM_MAX];
> +     bool mst_active;
>  };
>  
>  static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, 
> u32 offset)
> @@ -227,6 +228,32 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux 
> *aux,
>       return 0;
>  }
>  
> +void msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl)
> +{
> +     struct msm_dp_ctrl_private *ctrl;
> +     bool act_complete;
> +
> +     ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, 
> msm_dp_ctrl);
> +
> +     if (!ctrl->mst_active)
> +             return;
> +
> +     msm_dp_write_link(ctrl, REG_DP_MST_ACT, 0x1);
> +     /* make sure ACT signal is performed */
> +     wmb();
> +
> +     msleep(20); /* needs 1 frame time */
> +
> +     act_complete = msm_dp_read_link(ctrl, REG_DP_MST_ACT);
> +
> +     if (!act_complete)
> +             drm_dbg_dp(ctrl->drm_dev, "mst ACT trigger complete SUCCESS\n");
> +     else
> +             drm_dbg_dp(ctrl->drm_dev, "mst ACT trigger complete failed\n");

Shouldn't it return an error if the register dind't latch? Also,
shouldn't we set mst_active only if the write went through?

> +
> +     return;
> +}
> +
>  /*
>   * NOTE: resetting DP controller will also clear any pending HPD related 
> interrupts
>   */
> @@ -2079,6 +2106,8 @@ static int msm_dp_ctrl_link_maintenance(struct 
> msm_dp_ctrl_private *ctrl)
>  
>       msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO);
>  
> +     msm_dp_ctrl_mst_send_act(&ctrl->msm_dp_ctrl);
> +
>       ret = msm_dp_ctrl_wait4video_ready(ctrl);
>  end:
>       return ret;
> @@ -2275,7 +2304,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct 
> msm_dp_ctrl_private *ctrl
>       msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id);
>       msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl);
>  
> -     ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl);
> +     ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, false);
>       if (ret) {
>               DRM_ERROR("failed to enable DP link controller\n");
>               return ret;
> @@ -2355,7 +2384,7 @@ static bool msm_dp_ctrl_channel_eq_ok(struct 
> msm_dp_ctrl_private *ctrl)
>       return drm_dp_channel_eq_ok(link_status, num_lanes);
>  }
>  
> -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl)
> +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active)
>  {
>       int rc = 0;
>       struct msm_dp_ctrl_private *ctrl;
> @@ -2373,6 +2402,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl)
>  
>       rate = ctrl->panel->link_info.rate;
>       pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock;
> +     ctrl->mst_active = mst_active;
>  
>       msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl);
>  
> @@ -2643,6 +2673,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl 
> *msm_dp_ctrl, struct msm_dp_panel *
>  
>       msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO);
>  
> +     msm_dp_ctrl_mst_send_act(msm_dp_ctrl);
> +
>       ret = msm_dp_ctrl_wait4video_ready(ctrl);
>       if (ret)
>               return ret;
> @@ -2682,6 +2714,8 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl 
> *msm_dp_ctrl)
>  
>       msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl);
>  
> +     ctrl->mst_active = false;
> +
>       dev_pm_opp_set_rate(ctrl->dev, 0);
>       msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
>  
> @@ -2849,6 +2883,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, 
> struct msm_dp_link *link
>       ctrl->link_base = link_base;
>       ctrl->mst2link_base = mst2link_base;
>       ctrl->mst3link_base = mst3link_base;
> +     ctrl->mst_active = false;
>  
>       ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream);
>       if (ret) {
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h 
> b/drivers/gpu/drm/msm/dp/dp_ctrl.h
> index 
> 2baf7a1ff44dd7139d2da86390121d5e7a063e9a..abf84ddf463638900684f2511549a593783d2247
>  100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
> @@ -16,7 +16,7 @@ struct msm_dp_ctrl {
>  
>  struct phy;
>  
> -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl);
> +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active);
>  int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct 
> msm_dp_panel *msm_dp_panel);
>  int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool 
> force_link_train);
>  void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl);
> @@ -50,5 +50,5 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl 
> *msm_dp_ctrl);
>  void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl);
>  
>  void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl);
> -
> +void msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl);
>  #endif /* _DP_CTRL_H_ */
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index 
> 562a5eccf3f08c5669cc7c2ad1268897e975d0c4..eeba73f81c5ce7929dac88f4b47ac3741659864b
>  100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -709,7 +709,7 @@ static int msm_dp_display_prepare(struct 
> msm_dp_display_private *dp)
>               force_link_train = true;
>       }
>  
> -     rc = msm_dp_ctrl_on_link(dp->ctrl);
> +     rc = msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active);
>       if (rc) {
>               DRM_ERROR("Failed link training (rc=%d)\n", rc);
>               msm_dp_display->connector->state->link_status = 
> DRM_LINK_STATUS_BAD;
> @@ -1557,6 +1557,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *dp)
>       msm_dp_display = container_of(dp, struct msm_dp_display_private, 
> msm_dp_display);
>  
>       msm_dp_ctrl_push_idle(msm_dp_display->ctrl);
> +     msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl);
>  }
>  
>  static void msm_dp_display_unprepare(struct msm_dp_display_private *dp)
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.h 
> b/drivers/gpu/drm/msm/dp/dp_display.h
> index 
> a839d0a3941eac3e277185e42fddea15ca05a17f..9442157bca9d63467b4c43fa644651ad2cbcbef5
>  100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.h
> +++ b/drivers/gpu/drm/msm/dp/dp_display.h
> @@ -21,6 +21,7 @@ struct msm_dp {
>       bool audio_enabled;
>       bool power_on;
>       bool prepared;
> +     bool mst_active;
>       unsigned int connector_type;
>       bool is_edp;
>       bool internal_hpd;
> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
> index 
> a806d397ff9d9ad3830b1f539614bffcc955a786..de3d0b8b52c269fd7575edf3f4096a4284ad0b8d
>  100644
> --- a/drivers/gpu/drm/msm/dp/dp_reg.h
> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
> @@ -158,6 +158,8 @@
>  #define DP_CONFIGURATION_CTRL_BPC_SHIFT              (0x08)
>  #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT        (0x0D)
>  
> +#define REG_DP_MST_ACT                               (0x00000500)
> +
>  #define REG_DP_SOFTWARE_MVID                 (0x00000010)
>  #define REG_DP_SOFTWARE_NVID                 (0x00000018)
>  #define REG_DP_TOTAL_HOR_VER                 (0x0000001C)
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

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