From: Abhinav Kumar <quic_abhin...@quicinc.com>
Use msm_dp_get_mst_intf_id() to get the interface ID for the DP MST
controller as the intf_id is unique for each MST stream of each
DP controller.
Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
Signed-off-by: Yongxing Mou <yongxing....@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 51 +++++++++++++++++++++++++----
1 file changed, 44 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index
05e5f3463e30c9a6bd5b740580720ae2bf6b3246..2eb5397d15732b224372c68d0b2b7167da9f2896
100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1429,17 +1429,52 @@ static void dpu_encoder_virt_atomic_disable(struct
drm_encoder *drm_enc,
static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg
*catalog,
struct dpu_rm *dpu_rm,
- enum dpu_intf_type type, u32 controller_id)
+ enum dpu_intf_type type, int enc_type, u32 id)
{
- int i = 0;
+ int i = 0, cnt = 0;
+ int controller_id = id >> 16;
+ int stream_id = id & 0x0F;
if (type == INTF_WB)
return NULL;
- for (i = 0; i < catalog->intf_count; i++) {
- if (catalog->intf[i].type == type
- && catalog->intf[i].controller_id == controller_id) {
- return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id);
+ if (enc_type == DRM_MODE_ENCODER_DPMST) {
+ /* The intf order in dpu_intf_cfg matches the mapping in the DP
HPG.
+ * example:
+ * DPU_8_4_0 - DP Controller intf to stream Mapping
+ *
+ * +-------------+----------+----------+----------+----------+
+ * | stream_id | 0 | 1 | 2 | 3 |
+ * +-------------+----------+----------+----------+----------+
+ * | DP0 | INTF_0 | INTF_3 | INTF_6 | INTF_7 |
+ * | DP1 | INTF_4 | INTF_8 | | |
+ * +-------------+----------+----------+----------+----------+
+ *
+ * DPU_9_2_0 - DP Controller intf to stream Mapping
+ *
+ * +-------------+----------+----------+
+ * | Controller | 0 | 1 |
+ * +-------------+----------+----------+
+ * | DP0 | INTF_0 | INTF_3 |
+ * | DP1 | INTF_4 | INTF_8 |
+ * | DP2 | INTF_6 | INTF_7 |
+ * +-------------+----------+----------+
+ */
+ DPU_DEBUG("controller_id %d for stream_id = %d\n",
controller_id, stream_id);
+ for (i = 0; i < catalog->intf_count; i++) {
+ if (catalog->intf[i].type == INTF_DP
+ && controller_id == catalog->intf[i].controller_id) {
+ if (cnt == stream_id)
+ return dpu_rm_get_intf(dpu_rm,
catalog->intf[i].id);
+ cnt++;
+ }
+ }
+ } else {
+ for (i = 0; i < catalog->intf_count; i++) {
+ if (catalog->intf[i].type == type
+ && catalog->intf[i].controller_id == controller_id) {
+ return dpu_rm_get_intf(dpu_rm,
catalog->intf[i].id);
+ }
}
}
@@ -2670,7 +2705,9 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog,
&dpu_kms->rm,
disp_info->intf_type,
- controller_id);
+
dpu_enc->base.encoder_type,
+ controller_id << 16
+ |
disp_info->stream_id);
if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm,
controller_id);
--
2.34.1
