On Wed, Aug 20, 2025 at 05:34:48PM +0800, Xiangxu Yin wrote:
> Introduce QCS615 hardware-specific configuration for DP PHY mode,
> including register offsets, initialization tables, voltage swing
> and pre-emphasis settings.
This will trigger unused warnings. Please squash this into the patch
adding compat string to the driver.
>
> Signed-off-by: Xiangxu Yin <xiangxu....@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 139
> +++++++++++++++++++++++++++++++
> 1 file changed, 139 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> index
> 6b0e86ec43ded3d850f68f248a74c39f74ecb5bb..61128d606238321d1b573655b3b987226aa2d594
> 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> @@ -284,6 +284,86 @@ static const struct qmp_phy_init_tbl
> qcm2290_usb3_pcs_tbl[] = {
> QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> };
>
> +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_CTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x2c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
> +};
> +
> +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4),
> +};
> +
> +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x70),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4),
> +};
> +
> +static const struct qmp_phy_init_tbl qcs615_qmp_dp_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x2b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x12),
> +};
> +
> enum qmp_phy_usbc_type {
> QMP_PHY_USBC_USB3_ONLY,
> QMP_PHY_USBC_USB3_DP,
> @@ -449,6 +529,34 @@ static const struct qmp_usbc_offsets
> qmp_usbc_offsets_v3_qcm2290 = {
> .rx2 = 0x800,
> };
>
> +static const struct qmp_usbc_offsets qmp_usbc_usb3dp_offsets_qcs615 = {
> + .serdes = 0x0,
> + .pcs = 0xc00,
> + .pcs_misc = 0xa00,
> + .tx = 0x200,
> + .rx = 0x400,
> + .tx2 = 0x600,
> + .rx2 = 0x800,
> + .dp_serdes = 0x1c00,
> + .dp_txa = 0x1400,
> + .dp_txb = 0x1800,
> + .dp_dp_phy = 0x1000,
> +};
> +
> +static const u8 qmp_dp_pre_emphasis_hbr2_rbr[4][4] = {
> + {0x00, 0x0b, 0x12, 0xff},
> + {0x00, 0x0a, 0x12, 0xff},
> + {0x00, 0x0c, 0xff, 0xff},
> + {0xff, 0xff, 0xff, 0xff}
> +};
> +
> +static const u8 qmp_dp_voltage_swing_hbr2_rbr[4][4] = {
> + {0x07, 0x0f, 0x14, 0xff},
> + {0x11, 0x1d, 0x1f, 0xff},
> + {0x18, 0x1f, 0xff, 0xff},
> + {0xff, 0xff, 0xff, 0xff}
> +};
> +
> static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
> .offsets = &qmp_usbc_offsets_v3_qcm2290,
> .type = QMP_PHY_USBC_USB3_ONLY,
> @@ -500,6 +608,37 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg = {
> .regs = qmp_v3_usb3phy_regs_layout_qcm2290,
> };
>
> +static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = {
> + .offsets = &qmp_usbc_usb3dp_offsets_qcs615,
> + .type = QMP_PHY_USBC_USB3_DP,
> +
> + .serdes_tbl = qcm2290_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
> + .tx_tbl = qcm2290_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
> + .rx_tbl = qcm2290_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
> + .pcs_tbl = qcm2290_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
> +
> + .regs = qmp_v3_usb3phy_regs_layout_qcm2290,
> +
> + .dp_serdes_tbl = qcs615_qmp_dp_serdes_tbl,
> + .dp_serdes_tbl_num = ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl),
> + .dp_tx_tbl = qcs615_qmp_dp_tx_tbl,
> + .dp_tx_tbl_num = ARRAY_SIZE(qcs615_qmp_dp_tx_tbl),
> +
> + .serdes_tbl_rbr = qcs615_qmp_dp_serdes_tbl_rbr,
> + .serdes_tbl_rbr_num = ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_rbr),
> + .serdes_tbl_hbr = qcs615_qmp_dp_serdes_tbl_hbr,
> + .serdes_tbl_hbr_num = ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr),
> + .serdes_tbl_hbr2 = qcs615_qmp_dp_serdes_tbl_hbr2,
> + .serdes_tbl_hbr2_num = ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr2),
> +
> + .swing_tbl = &qmp_dp_voltage_swing_hbr2_rbr,
> + .pre_emphasis_tbl = &qmp_dp_pre_emphasis_hbr2_rbr,
> +};
> +
> static int qmp_usbc_com_init(struct phy *phy)
> {
> struct qmp_usbc *qmp = phy_get_drvdata(phy);
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
