On 8/14/25 7:39 AM, Tomi Valkeinen wrote:
Hello Tomi,
The 1/2/3 lane mode was already implemented in the driver, except it was
broken.
If it never worked, was it broken or not implemented? How much code the
original driver must have for the feature to have the feature
"implemented, just broken"?
I believe the code was all there, and the lane count could be
configured, it simply never worked. That's why I think the lane count
was implemented, but broken.
If it reads the num lanes from the DT, and
allows the driver to probe with 1-4 lanes, is it then "implemented, but
broken"? Or does the driver have to have a clear intent on having the
feature (even if it doesn't work) for it to be implemented?
If it was not implemented, then the lane count from DT should have been
checked and if it was != 4, such configuration should have been rejected.
I'm not trying to be annoying here, and I'm fine with the new patch you
sent. I bring this topic up as I just had a similar discussion in a
thread for another patch series, and the answer is not clear to me.
stable-kernel-rules.rst doesn't really cover this case, so, afaics,
someone could argue that this (well, the new one you sent) is not valid
stable patch: it doesn't fix a crash/hang/etc, it adds support for more
lane setups.
In this particular case I'm fine calling this a fix, and backporting to
stable, as the patch is such a small one and "obviously correct" (as
stable-kernel-rules.rst says) because with the only working lane setup,
4-lanes, we can easily see that the values written to registers are
identical to default/old values.
Still, if someone has feedback on how to approach this question, I
wouldn't mind hearing the thoughts =).
See above why I think this is a fix, maybe it helps.
You say they "fix", but they're not quite fixes either. The
patch 3 could be considered a fix, but at the moment it just writes the
default value to the register, so no point in marking it as a fix to be
backported.
3/4 does write the DSI lane count into TXSETR , not the default value.
I meant that as only the 4-lane mode works, I must assume all the users
use 4-lane mode.
Yes, that is currently the case.
Thus with patch 3, a value identical to the default
value gets written, as everyone uses 4 lanes. So, if it's backported to
kernels where everyone uses 4 lanes, it won't change anything.
Correct.
