[PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps

[payne . lin]

From: Bincai Liu <bincai....@mediatek.com>

Mipi dphy can support up to 4k30 without dsc.

Signed-off-by: Bincai Liu <bincai....@mediatek.com>
Signed-off-by: Payne Lin <payne....@mediatek.com>
---
 drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c 
b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
index 553725e1269c..b8233c496070 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
@@ -100,7 +100,7 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
                                       unsigned long *prate)
 {
-       return clamp_val(rate, 125000000, 1600000000);
+       return clamp_val(rate, 125000000, 2500000000);
 }
 
 static const struct clk_ops mtk_mipi_tx_pll_ops = {
-- 
2.45.2