Hi Dave,
On 07/08/25 10:28, Dave Stevenson wrote:
There are now formats defined for 2-plane YUV420 at 10, 12,
and 16 bit depth using the most significant bits of the 16bit
word (P010, P012, and P016), and 3-plane YUV420 at those
depths using the least significant bits of the 16 bit word
(S010, S012, and S016).
VC4_GEN_6 can support all those formats although only using
at most 10bits of resolution.
Add them as supported formats for all planes, but filtered
by hardware revision.
Signed-off-by: Dave Stevenson <dave.steven...@raspberrypi.com>
Acked-by: Maíra Canal <mca...@igalia.com>
Best Regards,
- Maíra
---
drivers/gpu/drm/vc4/vc4_plane.c | 42 +++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/vc4/vc4_regs.h | 9 +++++++++
2 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 3bdd9466a7b0..5fc26f705425 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -247,6 +247,42 @@ static const struct hvs_format {
.pixel_order = HVS_PIXEL_ORDER_BGRA,
.pixel_order_hvs5 = HVS_PIXEL_ORDER_RGBA,
},
+ {
+ .drm = DRM_FORMAT_P010,
+ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_2PLANE,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
+ .min_gen = VC4_GEN_6_C,
+ },
+ {
+ .drm = DRM_FORMAT_P012,
+ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_2PLANE,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
+ .min_gen = VC4_GEN_6_C,
+ },
+ {
+ .drm = DRM_FORMAT_P016,
+ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_2PLANE,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
+ .min_gen = VC4_GEN_6_C,
+ },
+ {
+ .drm = DRM_FORMAT_S010,
+ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_9_0_3PLANE,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
+ .min_gen = VC4_GEN_6_C,
+ },
+ {
+ .drm = DRM_FORMAT_S012,
+ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_11_2_3PLANE,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
+ .min_gen = VC4_GEN_6_C,
+ },
+ {
+ .drm = DRM_FORMAT_S016,
+ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_3PLANE,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
+ .min_gen = VC4_GEN_6_C,
+ },
};
static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
@@ -2490,6 +2526,12 @@ static bool vc4_format_mod_supported(struct drm_plane
*plane,
case DRM_FORMAT_YVU420:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ case DRM_FORMAT_S010:
+ case DRM_FORMAT_S012:
+ case DRM_FORMAT_S016:
default:
return (modifier == DRM_FORMAT_MOD_LINEAR);
}
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 27158be19952..4536e3c0533b 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -1079,6 +1079,15 @@ enum hvs_pixel_format {
HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
HVS_PIXEL_FORMAT_RGBA1010102 = 16,
HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
+ /* 10 bit YUV420 formats with data with various alignments */
+ HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_2PLANE = 24,
+ HVS_PIXEL_FORMAT_YCBCR_YUV420_15_6_3PLANE = 25,
+ HVS_PIXEL_FORMAT_YCBCR_YUV420_13_4_2PLANE = 26,
+ HVS_PIXEL_FORMAT_YCBCR_YUV420_13_4_3PLANE = 27,
+ HVS_PIXEL_FORMAT_YCBCR_YUV420_11_2_2PLANE = 28,
+ HVS_PIXEL_FORMAT_YCBCR_YUV420_11_2_3PLANE = 29,
+ HVS_PIXEL_FORMAT_YCBCR_YUV420_9_0_2PLANE = 30,
+ HVS_PIXEL_FORMAT_YCBCR_YUV420_9_0_3PLANE = 31,
};
/* Note: the LSB is the rightmost character shown. Only valid for
