Hi Ethan, kernel test robot noticed the following build errors:
[auto build test ERROR on b9ddaa95fd283bce7041550ddbbe7e764c477110] url: https://github.com/intel-lab-lkp/linux/commits/Ethan-Carter-Edwards/drm-nouveau-gsp-remove-always-true-if-check/20250802-095804 base: b9ddaa95fd283bce7041550ddbbe7e764c477110 patch link: https://lore.kernel.org/r/20250801-nouveau-fifo-v1-1-25b9db5283bc%40ethancedwards.com patch subject: [PATCH] drm/nouveau/gsp: remove always true if check config: i386-buildonly-randconfig-004-20250802 (https://download.01.org/0day-ci/archive/20250802/202508021705.k0nkiqga-...@intel.com/config) compiler: gcc-12 (Debian 12.2.0-14+deb12u1) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250802/202508021705.k0nkiqga-...@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <l...@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202508021705.k0nkiqga-...@intel.com/ All errors (new ones prefixed by >>): drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c: In function 'r535_chan_ramfc_write': >> drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c:193:34: error: >> conflicting types for 'ctrl'; have 'NVA06F_CTRL_BIND_PARAMS *' 193 | NVA06F_CTRL_BIND_PARAMS *ctrl; | ^~~~ drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c:191:45: note: previous declaration of 'ctrl' with type 'NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *' 191 | NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *ctrl; | ^~~~ >> drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c:211:13: error: >> 'NVA06F_CTRL_BIND_PARAMS' has no member named 'bEnable' 211 | ctrl->bEnable = 1; | ^~ vim +193 drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 152 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 153 static int 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 154 r535_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 155 { 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 156 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 157 struct nvkm_engn *engn; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 158 struct nvkm_device *device = fifo->engine.subdev.device; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 159 const struct nvkm_rm_api *rmapi = device->gsp->rm->api; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 160 u32 eT = ~0; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 161 int ret; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 162 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 163 if (unlikely(device->gr && !device->gr->engine.subdev.oneinit)) { 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 164 ret = nvkm_subdev_oneinit(&device->gr->engine.subdev); 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 165 if (ret) 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 166 return ret; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 167 } 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 168 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 169 nvkm_runl_foreach_engn(engn, chan->cgrp->runl) { 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 170 eT = engn->id; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 171 break; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 172 } 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 173 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 174 if (WARN_ON(eT == ~0)) 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 175 return -EINVAL; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 176 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 177 chan->rm.mthdbuf.ptr = dma_alloc_coherent(fifo->engine.subdev.device->dev, 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 178 fifo->rm.mthdbuf_size, 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 179 &chan->rm.mthdbuf.addr, GFP_KERNEL); 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 180 if (!chan->rm.mthdbuf.ptr) 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 181 return -ENOMEM; 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 182 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 183 ret = rmapi->fifo->chan.alloc(&chan->vmm->rm.device, NVKM_RM_CHAN(chan->id), 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 184 eT, chan->runq, priv, chan->id, chan->inst->addr, 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 185 nvkm_memory_addr(chan->userd.mem) + chan->userd.base, 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 186 chan->rm.mthdbuf.addr, chan->vmm, offset, length, 27b13dc5d0515e drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c Ben Skeggs 2024-11-20 187 &chan->rm.object); 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 188 if (ret) 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 189 return ret; 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 190 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 191 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *ctrl; 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 192 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 @193 NVA06F_CTRL_BIND_PARAMS *ctrl; 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 194 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 195 ctrl = nvkm_gsp_rm_ctrl_get(&chan->rm.object, 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 196 NVA06F_CTRL_CMD_BIND, sizeof(*ctrl)); 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 197 if (WARN_ON(IS_ERR(ctrl))) 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 198 return PTR_ERR(ctrl); 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 199 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 200 ctrl->engineType = eT; 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 201 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 202 ret = nvkm_gsp_rm_ctrl_wr(&chan->rm.object, ctrl); 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 203 if (ret) 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 204 return ret; 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 205 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 206 ctrl = nvkm_gsp_rm_ctrl_get(&chan->rm.object, 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 207 NVA06F_CTRL_CMD_GPFIFO_SCHEDULE, sizeof(*ctrl)); 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 208 if (WARN_ON(IS_ERR(ctrl))) 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 209 return PTR_ERR(ctrl); 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 210 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 @211 ctrl->bEnable = 1; 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 212 ret = nvkm_gsp_rm_ctrl_wr(&chan->rm.object, ctrl); 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 213 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 214 return ret; 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 215 } 2a77d015b53886 drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c Ben Skeggs 2023-09-19 216 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
