On Wed, Jul 30, 2025 at 06:09:38PM +0530, Ayushi Makhija wrote:
> Currently, the high bitfield of certain DSI registers
> do not align with the configuration of the SWI registers
> description. This can lead to wrong programming these DSI
> registers, for example for 4k resloution where H_TOTAL is
> taking 13 bits but software is programming only 12 bits
> because of the incorrect bitmask for H_TOTAL bitfeild,
> this is causing DSI FIFO errors. To resolve this issue,
> increase the high bitfield of the DSI registers from 12 bits
> to 16 bits in dsi.xml to match the SWI register configuration.
>
Fixes: 4f52f5e63b62 ("drm/msm: import XML display registers database")
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com>
> Signed-off-by: Ayushi Makhija <quic_amakh...@quicinc.com>
> ---
> drivers/gpu/drm/msm/registers/display/dsi.xml | 28 +++++++++----------
> 1 file changed, 14 insertions(+), 14 deletions(-)
--
With best wishes
Dmitry
