From: Andy Yan <andy....@rock-chips.com>
There are two DW DPTX based DisplayPort Controller on rk3588 which are compliant with the DisplayPort Specification Version 1.4 with the following features: * DisplayPort 1.4a * Main Link: 1/2/4 lanes * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps * AUX channel 1Mbps * Single Stream Transport(SST) * Multistream Transport (MST) * Type-C support (alternate mode) * HDCP 2.2, HDCP 1.3 * Supports up to 8/10 bits per color component * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0 * Pixel clock up to 594MHz * I2S, SPDIF audio interface The current version of this patch series only supports basic display outputs. I conducted tests with DP0 in 1080p and 4K@60 YCbCr4:2:0 modes; the ALT/Type-C mode was tested on Rock 5B, DP1 was tested on Rock 5 ITX by Stephen and Piotr. HDCP and audio features remain unimplemented. For RK3588, it's only support SST, while in the upcoming RK3576, it can support MST output. Changes in v5: - Use drm_dp_read_sink_count_cap instead of the private implementation. - Add MAINTAINERS entry. - Link to v4: https://lore.kernel.org/linux-rockchip/20250619063900.700491-1-andys...@163.com/ Changes in v4: - Drop unnecessary header files - Switch to devm_drm_bridge_alloc - Drop unused function - Add platform_set_drvdata - Link to v3: https://lore.kernel.org/linux-rockchip/20250403033748.245007-1-andys...@163.com/ Changes in v3: - Rebase on drm-misc-next - Switch to common helpers to power up/down dp link - Only pass parameters to phy that should be set - First introduced in this version. - First introduced in this version. - Add RA620 into bridge chain. - Link to v2: https://lore.kernel.org/linux-rockchip/20250312104214.525242-1-andys...@163.com/ Changes in v2: - Link to V1: https://lore.kernel.org/linux-rockchip/20250223113036.74252-1-andys...@163.com/ - Fix a character encoding issue - Fix compile error when build as module - Add phy init - Only use one dw_dp_link_train_set - inline dw_dp_phy_update_vs_emph - Use dp_sdp - Check return value of drm_modeset_lock - Merge code in atomic_pre_enable/mode_fixup to atomic_check - Return NULL if can't find a supported output format - Fix max_link_rate from plat_data - no include uapi path - switch to drmm_encoder_init - Sort in alphabetical order Andy Yan (10): dt-bindings: display: rockchip: Add schema for RK3588 DPTX Controller drm/bridge: synopsys: Add DW DPTX Controller support library drm/rockchip: Add RK3588 DPTX output support MAINTAINERS: Add entry for DW DPTX Controller bridge dt-bindings: display: simple-bridge: Add ra620 compatible drm/birdge: simple-bridge: Add support for radxa ra620 arm64: dts: rockchip: Add DP0 for rk3588 arm64: dts: rockchip: Add DP1 for rk3588 arm64: dts: rockchip: Enable DisplayPort for rk3588s Cool Pi 4B arm64: dts: rockchip: Enable DP2HDMI for ROCK 5 ITX .../display/bridge/simple-bridge.yaml | 1 + .../display/rockchip/rockchip,dw-dp.yaml | 150 ++ MAINTAINERS | 8 + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 30 + .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 + .../boot/dts/rockchip/rk3588-rock-5-itx.dts | 59 + .../boot/dts/rockchip/rk3588s-coolpi-4b.dts | 37 + drivers/gpu/drm/bridge/simple-bridge.c | 5 + drivers/gpu/drm/bridge/synopsys/Kconfig | 7 + drivers/gpu/drm/bridge/synopsys/Makefile | 1 + drivers/gpu/drm/bridge/synopsys/dw-dp.c | 2044 +++++++++++++++++ drivers/gpu/drm/rockchip/Kconfig | 9 + drivers/gpu/drm/rockchip/Makefile | 1 + drivers/gpu/drm/rockchip/dw_dp-rockchip.c | 150 ++ drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 + drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + include/drm/bridge/dw_dp.h | 20 + 17 files changed, 2554 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-dp.c create mode 100644 drivers/gpu/drm/rockchip/dw_dp-rockchip.c create mode 100644 include/drm/bridge/dw_dp.h -- 2.43.0 base-commit: 6085a45a069d2aeab6bb3e5f3fdd32e259703106 branch: rk3588-dp-upstream-v5
