Hello Piotr, At 2025-06-29 02:11:00, "Piotr Zalewski" <pz010001011...@proton.me> wrote: >Make video port registers nonvolatile. As DSP_CTRL register is written >to twice due to gamma LUT enable bit which is set outside of the main >DSP_CTRL initialization within atomic_enable (for rk356x case it is also >necesarry to always disable gamma LUT before writing a new LUT) there is >a chance that DSP_CTRL value read-out in gamma LUT init/update code is >not the one which was written by the preceding DSP_CTRL initialization >code within atomic_enable. This might result in misconfigured DSP_CTRL >which leads to no visual output[1]. Since DSP_CTRL write takes effect >after VSYNC[1] the issue is not always present. When tested on Pinetab2 >with kernel 6.14 it happenes only when DRM is compiled as a module[1]. >In order to confirm that it is because of timing I inserted 18ms udelay >before vop2_crtc_atomic_try_set_gamma in atomic enable and compiled DRM >as module - this has also fixed the issue on Pinetab2. > >[1] >https://lore.kernel.org/linux-rockchip/562b38e5.a496.1975f09f983.coremail.andys...@163.com/ > >Reported-by: Diederik de Haas <didi.deb...@cknow.org> >Closes: >https://lore.kernel.org/linux-rockchip/daevdstmwi1e.j454vzn0r...@cknow.org/ >Suggested-by: Andy Yan <andy....@rock-chips.com> >Signed-off-by: Piotr Zalewski <pz010001011...@proton.me> >--- > drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > >diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c >b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c >index d0f5fea15e21..241060cc24cb 100644 >--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c >+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c >@@ -2589,12 +2589,13 @@ static int vop2_win_init(struct vop2 *vop2) > } > > /* >- * The window registers are only updated when config done is written. >- * Until that they read back the old value. As we read-modify-write >- * these registers mark them as non-volatile. This makes sure we read >- * the new values from the regmap register cache. >+ * The window and video port registers are only updated when config >+ * done is written. Until that they read back the old value. As we >+ * read-modify-write these registers mark them as non-volatile. This >+ * makes sure we read the new values from the regmap register cache. > */ > static const struct regmap_range vop2_nonvolatile_range[] = { >+ regmap_reg_range(RK3568_VP0_CTRL_BASE, RK3588_VP3_CTRL_BASE+255),
Small nit: there should be spaces before and after the + > regmap_reg_range(0x1000, 0x23ff), > }; > >-- >2.50.0 > >
