Am Dienstag, dem 03.06.2025 um 06:37 +1000 schrieb Dave Airlie: > On Mon, 2 Jun 2025 at 21:51, Christian König <christian.koe...@amd.com> wrote: > > [...] > > > > > Has anyone else come across this problem with TTM on aarch64? or > > > understand if I'm missing something. > > > > If I'm not completely mistaken both pgprot_dmacoherent and > > pgprot_writecombine map to MT_NORMAL_NC because there is no such thing as > > uncached system memory without write combining on aarch64. > > > > I mean why would you want to do this except for getting the MMIO write > > ordering right? Avoiding write memory barriers? > > I'm not 100% sure why tegra does it in the first place, I suspect > working around lack of knowledge on what is correct and just hey this > works, so move on. > As long as you directly map the pages in RAM writecombine is absolutely fine for Tegra. However, at some point the Tegra implementation did map BOs through the "VRAM" access BAR of the GPU, which isn't able to deal with bufferable mappings for some reason (at least that was the case on GK20A). I'm not sure how things are working right now, it's a long time since I last looked into this code.
Regards, Lucas
