On Thu, May 15, 2025 at 04:33:37PM +0300, Alexander Usyskin wrote:
> In intel-dg, there is no access to the spi controller,
> the information is extracted from the descriptor region.
...
> +static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *device)
> +{
> + int ret;
> + unsigned int i, n;
> + u32 access_map = 0;
Reverse xmas order (along with all other places) and
Reviewed-by: Raag Jadav <raag.ja...@intel.com>
> + /* clean error register, previous errors are ignored */
> + idg_nvm_error(nvm);
> +
> + ret = idg_nvm_is_valid(nvm);
> + if (ret) {
> + dev_err(device, "The MEM is not valid %d\n", ret);
> + return ret;
> + }
> +
> + if (idg_nvm_get_access_map(nvm, &access_map))
> + return -EIO;
> +
> + for (i = 0, n = 0; i < nvm->nregions; i++) {
> + u32 address, base, limit, region;
> + u8 id = nvm->regions[i].id;
> +
> + address = NVM_FLREG(id);
> + region = idg_nvm_read32(nvm, address);
> +
> + base = FIELD_GET(NVM_FREG_BASE_MASK, region) <<
> NVM_FREG_ADDR_SHIFT;
> + limit = (FIELD_GET(NVM_FREG_ADDR_MASK, region) <<
> NVM_FREG_ADDR_SHIFT) |
> + NVM_FREG_MIN_REGION_SIZE;
> +
> + dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit:
> 0x%08x\n",
> + id, nvm->regions[i].name, region, base, limit);
> +
> + if (base >= limit || (i > 0 && limit == 0)) {
> + dev_dbg(device, "[%d] %s: disabled\n",
> + id, nvm->regions[i].name);
> + nvm->regions[i].is_readable = 0;
> + continue;
> + }
> +
> + if (nvm->size < limit)
> + nvm->size = limit;
> +
> + nvm->regions[i].offset = base;
> + nvm->regions[i].size = limit - base + 1;
> + /* No write access to descriptor; mask it out*/
> + nvm->regions[i].is_writable =
> idg_nvm_region_writable(access_map, id);
> +
> + nvm->regions[i].is_readable =
> idg_nvm_region_readable(access_map, id);
> + dev_dbg(device, "Registered, %s id=%d offset=%lld size=%lld
> rd=%d wr=%d\n",
> + nvm->regions[i].name,
> + nvm->regions[i].id,
> + nvm->regions[i].offset,
> + nvm->regions[i].size,
> + nvm->regions[i].is_readable,
> + nvm->regions[i].is_writable);
> +
> + if (nvm->regions[i].is_readable)
> + n++;
> + }
> +
> + dev_dbg(device, "Registered %d regions\n", n);
> +
> + /* Need to add 1 to the amount of memory
> + * so it is reported as an even block
> + */
> + nvm->size += 1;
> +
> + return n;
> +}
> +
> static void intel_dg_nvm_release(struct kref *kref)
> {
> struct intel_dg_nvm *nvm = container_of(kref, struct intel_dg_nvm,
> refcnt);
> @@ -85,6 +285,12 @@ static int intel_dg_mtd_probe(struct auxiliary_device
> *aux_dev,
> goto err;
> }
>
> + ret = intel_dg_nvm_init(nvm, device);
> + if (ret < 0) {
> + dev_err(device, "cannot initialize nvm %d\n", ret);
> + goto err;
> + }
> +
> dev_set_drvdata(&aux_dev->dev, nvm);
>
> return 0;
> --
> 2.43.0
>
