As discussed a lot in the past, the UBWC config must be coherent across a number of IP blocks (currently display and GPU, but it also may/will concern camera/video as the drivers evolve).
So far, we've been trying to keep the values reasonable in each of the two drivers separately, but it really make sense to do so, especially given certain fields (see [1]) may need to be gathered dynamically. This series introduces a Single Source of Truth (SSOT) database to be consumed by multimedia drivers as needed. [1] https://lore.kernel.org/linux-arm-msm/20250410-topic-smem_dramc-v2-0-dead15264...@oss.qualcomm.com/ Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com> --- Changes in v2: - Rearrange some patches - Don't zeroalloc a copy of ubwc_config, store a full struct inside adreno_gpu instead (temporary solution until we trust the central db on the HBB value) - Improve some commit messages - Fix up SM6125's config - Don't break userspace abi (hbb value) - Don't keep mdss_reg_bus_bw in ubwc_config - Add the last patch warning if there are inconsistencies (I don't insist on it getting merged, but I think it's a good idea for the time being) - Link to v1: https://lore.kernel.org/r/20250508-topic-ubwc_central-v1-0-035c4c5cb...@oss.qualcomm.com --- Konrad Dybcio (15): soc: qcom: Add UBWC config provider drm/msm: Offset MDSS HBB value by 13 drm/msm: Use the central UBWC config database drm/msm/a6xx: Get a handle to the common UBWC config drm/msm/a6xx: Resolve the meaning of AMSBC drm/msm/a6xx: Simplify uavflagprd_inv detection drm/msm/a6xx: Resolve the meaning of UBWC_MODE drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calc drm/msm/a6xx: Resolve the meaning of rgb565_predicator drm/msm/a6xx: Simplify min_acc_len calculation drm/msm/adreno: Switch to the common UBWC config struct drm/msm/a6xx: Drop cfg->ubwc_swizzle override soc: qcom: ubwc: Fix SM6125's ubwc_swizzle value soc: qcom: ubwc: Add #defines for UBWC swizzle bits [RFC] drm/msm/a6xx: Warn if the highest_bank_bit value is overwritten drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 20 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 131 +++++------ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +- drivers/gpu/drm/msm/msm_mdss.c | 333 +++++----------------------- drivers/gpu/drm/msm/msm_mdss.h | 28 --- drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ubwc_config.c | 244 ++++++++++++++++++++ include/linux/soc/qcom/ubwc.h | 69 ++++++ 18 files changed, 480 insertions(+), 433 deletions(-) --- base-commit: edef457004774e598fc4c1b7d1d4f0bcd9d0bb30 change-id: 20250430-topic-ubwc_central-53c540f019e5 Best regards, -- Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
