On 2025-04-24 14:56:08 [+0800], Junxiao Chang wrote:
> MEI GSC interrupt comes from i915. It has top half and bottom half.
> Top half is called from i915 interrupt handler. It should be in
> irq disabled context.
> 
> With RT kernel, by default i915 IRQ handler is in threaded IRQ. MEI GSC
> top half might be in threaded IRQ context. In this case, local IRQ
> should be disabled for MEI GSC interrupt top half.
> 
> This change fixes A380/A770 GPU boot hang issue with RT kernel.

This should have a Fixes when generic_handle_irq() was introduced. 

> Signed-off-by: Junxiao Chang <junxiao.ch...@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gsc.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
> b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index 1e925c75fb080..9c72117263f78 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -270,6 +270,9 @@ static void gsc_init_one(struct drm_i915_private *i915, 
> struct intel_gsc *gsc,
>  static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
>  {
>       int ret;
> +#ifdef CONFIG_PREEMPT_RT
> +     int irq_disabled_flag;
> +#endif
>  
>       if (intf_id >= INTEL_GSC_NUM_INTERFACES) {
>               gt_warn_once(gt, "GSC irq: intf_id %d is out of range", 
> intf_id);
> @@ -284,7 +287,18 @@ static void gsc_irq_handler(struct intel_gt *gt, 
> unsigned int intf_id)
>       if (gt->gsc.intf[intf_id].irq < 0)
>               return;
>  
> +#ifdef CONFIG_PREEMPT_RT
> +     /* mei interrupt top half should run in irq disabled context */
> +     irq_disabled_flag = irqs_disabled();
> +     if (!irq_disabled_flag)
> +             local_irq_disable();
> +#endif
>       ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);

What about generic_handle_irq_safe() instead the whole ifdef show?

> +#ifdef CONFIG_PREEMPT_RT
> +     if (!irq_disabled_flag)
> +             local_irq_enable();
> +#endif
> +
>       if (ret)
>               gt_err_ratelimited(gt, "error handling GSC irq: %d\n", ret);
>  }

Sebastian

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