On Mon, Mar 24, 2025 at 02:29:37PM +0100, Andi Shyti wrote:
When setting the CCS mode, we mistakenly used wa_masked_en() to
apply the workaround, which reads from the register and masks the
existing value with the new one.
That's not what wa_masked_* does. The use of wa_masked* depends if the
register is a "masked register", which depends only on the HW IP, it's
not a sw thing.
On the xe side we tried to clarify this by making sure the
"masked" annotation is on the register definition rather than simply
using a different function that receives the same type:
drivers/gpu/drm/xe/regs/xe_gt_regs.h:#define CCS_MODE XE_REG(0x14804,
XE_REG_OPTION_MASKED)
Copy and paste of the comment from drivers/gpu/drm/i915/gt/intel_workarounds.c
that explains what it actually is:
/*
* WA operations on "masked register". A masked register has the upper 16 bits
* documented as "masked" in b-spec. Its purpose is to allow writing to just a
* portion of the register without a rmw: you simply write in the upper 16 bits
* the mask of bits you are going to modify.
*
* The wa_masked_* family of functions already does the necessary operations to
* calculate the mask based on the parameters passed, so user only has to
* provide the lower 16 bits of that register.
*/
If you don't set the bit on the upper nibble, it's the same as not
writing anything, so this patch basically breaks the setting to
CCS_MODE: none of the writes will go through.
bspec 46034 shows this register as a masked register:
Access: Masked(R/W)
and documentation for bits 31:16 shows the mask.
Lucas De Marchi
