On 2025-04-21 10:16, Dmitry Baryshkov wrote:
On Mon, Apr 21, 2025 at 05:09:22AM +0200, Barnabás Czémán wrote:
Sort adreno clocks in alphabetical order.
Why? The order of the clocks here matches the order in which they
should
be brought up.
Simple misunderstanding from previous attempts of documenting the
alwayson clock.
By the way i have find out a508/a509/a512 clock bring up order is
different from downstream.
Upstream: iface, rbmmtimer, mem, mem_iface, rbcpr, core
Downstream: core, iface, rbmmtimer, mem, alt_mem_iface, rbcpr
https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/arch/arm/boot/dts/qcom/sdm630-gpu.dtsi#L85
https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi#L87
Should I fix it?
Signed-off-by: Barnabás Czémán <barnabas.cze...@mainlining.org>
---
arch/arm64/boot/dts/qcom/msm8953.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi
b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index
4793a60fa946195d3220b6c44dec170d443f56db..8a7e80c959fad09f950fe202eba76d3aae01d1ea
100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -1052,18 +1052,18 @@ gpu: gpu@1c00000 {
reg-names = "kgsl_3d0_reg_memory";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
+ clocks = <&gcc GCC_BIMC_GPU_CLK>,
+ <&gcc GCC_OXILI_AON_CLK>,
+ <&gcc GCC_OXILI_GFX3D_CLK>,
<&gcc GCC_OXILI_AHB_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
- <&gcc GCC_BIMC_GPU_CLK>,
- <&gcc GCC_OXILI_TIMER_CLK>,
- <&gcc GCC_OXILI_AON_CLK>;
- clock-names = "core",
+ <&gcc GCC_OXILI_TIMER_CLK>;
+ clock-names = "alt_mem_iface",
+ "alwayson",
+ "core",
"iface",
"mem_iface",
- "alt_mem_iface",
- "rbbmtimer",
- "alwayson";
+ "rbbmtimer";
power-domains = <&gcc OXILI_GX_GDSC>;
iommus = <&gpu_iommu 0>;
--
2.49.0
