[PATCH v2 2/4] drm/msm/a5xx: Get HBB dynamically, if available

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>

The Highest Bank address Bit value can change based on memory type used.

Attempt to retrieve it dynamically, and fall back to a reasonable
default (the one used prior to this change) on error.

Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 
650e5bac225f372e819130b891f1d020b464f17f..c887d46c3a5798b7aa6813fc6e2575be1e715100
 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -9,6 +9,7 @@
 #include <linux/pm_opp.h>
 #include <linux/nvmem-consumer.h>
 #include <linux/slab.h>
+#include <linux/soc/qcom/smem.h>
 #include "msm_gem.h"
 #include "msm_mmu.h"
 #include "a5xx_gpu.h"
@@ -1758,7 +1759,11 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
        struct adreno_gpu *adreno_gpu;
        struct msm_gpu *gpu;
        unsigned int nr_rings;
-       int ret;
+       int hbb, ret;
+
+       /* We need data from SMEM to retrieve HBB below */
+       if (!qcom_smem_is_available())
+               return ERR_PTR(-EPROBE_DEFER);
 
        a5xx_gpu = kzalloc(sizeof(*a5xx_gpu), GFP_KERNEL);
        if (!a5xx_gpu)
@@ -1796,6 +1801,11 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
        else
                adreno_gpu->ubwc_config.highest_bank_bit = 14;
 
+       /* Attempt to retrieve HBB data from SMEM, keep the above defaults in 
case of error */
+       hbb = qcom_smem_dram_get_hbb();
+       if (hbb > 0)
+               adreno_gpu->ubwc_config.highest_bank_bit = hbb;
+
        /* a5xx only supports UBWC 1.0, these are not configurable */
        adreno_gpu->ubwc_config.macrotile_mode = 0;
        adreno_gpu->ubwc_config.ubwc_swizzle = 0x7;

-- 
2.49.0