From: Arnd Bergmann <a...@arndb.de>

clang-16 and earlier complain about what it thinks might be an out of
range number:

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c:348:8: error: call to 
__compiletime_assert_579 declared with 'error' attribute: FIELD_PREP: value too 
large for the field
                     PHY_SYS_RATIO(tmp));
                     ^
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c:90:27: note: expanded from macro 
'PHY_SYS_RATIO'
 #define PHY_SYS_RATIO(x)                FIELD_PREP(GENMASK(16, 0), x)

I could not figure out if that overflow is actually possible or not,
but truncating the range to the maximum value avoids the warning and
probably can't hurt.

Fixes: 0d6d86253fef ("drm/bridge/synopsys: Add MIPI DSI2 host controller 
bridge")
Signed-off-by: Arnd Bergmann <a...@arndb.de>
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
index 5fd7a459efdd..440b9a71012f 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi2.c
@@ -342,7 +342,7 @@ static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 
*dsi2)
        /*
         * SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / MIPI_DCPHY_HSCLK_Freq
         */
-       tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, sys_clk);
+       tmp = min(DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, sys_clk), GENMASK(16, 
0));
        regmap_write(dsi2->regmap, DSI2_PHY_SYS_RATIO_MAN_CFG,
                     PHY_SYS_RATIO(tmp));
 }
-- 
2.39.5

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