On Tue, Apr 08, 2025 at 09:40:36AM +0530, Arun R Murthy wrote:
> Minimum HBlank is programmed to address jitter for high resolutions with
> high refresh rates that have small Hblank, specifically where Hblank is
> smaller than one MTP.
I wondered if following the standard practice of one change per commit
is indeed not practical as you do it in this case.
>
> Signed-off-by: Arun R Murthy <arun.r.mur...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 78
> +++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 51 +------------------
> 2 files changed, 79 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index
> ea935a5d94c87202a68f84b28b0152835f47fe73..b73cb208a37c6d4928c1ce16d2ab689626dcbbc5
> 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -27,9 +27,11 @@
> #include <drm/drm_edid.h>
> #include <drm/drm_eld.h>
> #include <drm/drm_fixed.h>
> +#include <drm/display/drm_dp_helper.h>
> #include <drm/intel/i915_component.h>
>
> #include "i915_drv.h"
> +#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_audio.h"
> #include "intel_audio_regs.h"
> @@ -37,6 +39,8 @@
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> +#include "intel_dp.h"
> +#include "intel_dp_mst.h"
> #include "intel_lpe_audio.h"
>
> /**
> @@ -184,6 +188,62 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[]
> = {
> { 192000, TMDS_445_5M, 20480, 371250 },
> };
>
> +static void intel_audio_compute_min_hblank(struct intel_crtc_state
> *crtc_state,
> + struct drm_connector_state
> *conn_state)
I don't see any audio specific parameters in the calculation. This
function is also called for non-DP encoders (HDMI) and for DP encoders
it's called only if the DP sink supports audio.
Isn't it supposed to be a generic (not audio specific) DP state
calculated elsewhere (intel_dp.c)?
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> + int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
> + int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
Would be good to figure out and comment here what the 3 and 5 symbols
stand for.
> + bool is_dsc = crtc_state->dsc.compression_enable;
> + int bpp = is_dsc ? crtc_state->dsc.compressed_bpp_x16 :
> + crtc_state->pipe_bpp;
This looks incorrect as the units for compressed_bpp_x16 and pipe_bpp
are different.
> + bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> + u8 lane_count = crtc_state->lane_count;
> + int min_hblank, htotal, hactive;
I don't think it's worth adding separate variables for lane_count,
htotal, hactive.
> + int hactive_sym_cycles, htotal_sym_cycles;
> + int dsc_slices = intel_dp_mst_dsc_get_slice_count(connector,
> + crtc_state);
> +
> + if (DISPLAY_VER(display) < 30)
> + return;
> +
> + /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST &
> 128b/132b */
> + hactive = adjusted_mode->hdisplay;
> + htotal = adjusted_mode->htotal;
> +
> + hactive_sym_cycles = is_dsc ? drm_dp_link_dsc_symbol_cycles(lane_count,
To get LL instead of ML symbol cycles as required by bspec, you should
pass here lane_count=4 always, independent of the actual lane_count in
crtc_state.
> + hactive,
> + dsc_slices,
> + bpp,
> + symbol_size,
> + is_mst) :
> + drm_dp_link_symbol_cycles(lane_count,
> + hactive,
> + bpp,
This expects bpp_x16 units, but pipe_bpp that would be passed here has
different units.
> + symbol_size,
> + is_mst);
> + htotal_sym_cycles = htotal * hactive_sym_cycles / hactive;
> +
> + min_hblank = DIV_ROUND_UP((htotal_sym_cycles * bpp),
> + (4 * symbol_size)) - hactive_sym_cycles;
Not sure what the above division adjusts for, I think it should be just
min_hblank = htotal_sym_cycles - hactive_sym_cycles
> + /* minimum Hblank calculation:
> https://groups.vesa.org/wg/DP/document/20494 */
> + min_hblank = max(min_hblank, min_sym_cycles);
> +
> + /*
> + * adjust the BlankingStart/BlankingEnd framing control from
> + * the calculated value
> + */
> + min_hblank = min_hblank - 2;
> +
> + /* Maximum value to be programmed is limited to 10 */
> + min_hblank = min(10, min_hblank);
> + crtc_state->min_hblank = min_hblank;
> +}
> +
> +
> /*
> * WA_14020863754: Implement Audio Workaround
> * Corner case with Min Hblank Fix can cause audio hang
> @@ -715,6 +775,8 @@ bool intel_audio_compute_config(struct intel_encoder
> *encoder,
> memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld));
>
> crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
> +
> + intel_audio_compute_min_hblank(crtc_state, conn_state);
> mutex_unlock(&connector->eld_mutex);
>
> return true;
> @@ -778,6 +840,19 @@ void intel_audio_codec_enable(struct intel_encoder
> *encoder,
> intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld,
> crtc_state->port_clock,
> intel_crtc_has_dp_encoder(crtc_state));
> +
> + if (DISPLAY_VER(display) >= 30) {
> + /*
> + * Address issues for resolutions with high refresh rate that
> + * have small Hblank, specifically where Hblank is smaller than
> + * one MTP. Simulations indicate this will address the
> + * jitter issues that currently causes BS to be immediately
> + * followed by BE which DPRX devices are unable to handle.
> + * https://groups.vesa.org/wg/DP/document/20494
> + */
> + intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
> + crtc_state->min_hblank);
> + }
It's not clear why this programming is audio specific, based on my
earlier comment above.
> }
>
> /**
> @@ -834,6 +909,9 @@ void intel_audio_codec_disable(struct intel_encoder
> *encoder,
> }
>
> intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false);
> +
> + if (DISPLAY_VER(display) >= 30)
> + intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder), 0);
> }
>
> static void intel_acomp_get_config(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index
> af98a0d0e8376a79ce1ab6ff3c4f6af30f4d3e73..dae74c645c1a1d716504b7843fe1a5c8ace0d87d
> 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -211,26 +211,6 @@ int intel_dp_mst_dsc_get_slice_count(const struct
> intel_connector *connector,
> num_joined_pipes);
> }
>
> -static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state
> *crtc_state,
> - int bpp_x16)
> -{
> - struct intel_display *display = to_intel_display(crtc_state);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> - int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
> - int hblank;
> -
> - if (DISPLAY_VER(display) < 20)
> - return;
> -
> - /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST &
> 128b/132b */
> - hblank = DIV_ROUND_UP((DIV_ROUND_UP
> - (adjusted_mode->htotal -
> adjusted_mode->hdisplay, 4) * bpp_x16),
> - symbol_size);
> -
> - crtc_state->min_hblank = hblank;
> -}
> -
> int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state,
> @@ -301,8 +281,6 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp
> *intel_dp,
> local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state,
> false,
> dsc_slice_count, link_bpp_x16);
>
> - intel_dp_mst_compute_min_hblank(crtc_state, link_bpp_x16);
> -
> intel_dp_mst_compute_m_n(crtc_state,
> local_bw_overhead,
> link_bpp_x16,
> @@ -998,7 +976,6 @@ static void mst_stream_disable(struct intel_atomic_state
> *state,
> struct intel_dp *intel_dp = to_primary_dp(encoder);
> struct intel_connector *connector =
> to_intel_connector(old_conn_state->connector);
> - enum transcoder trans = old_crtc_state->cpu_transcoder;
>
> drm_dbg_kms(display->drm, "active links %d\n",
> intel_dp->mst.active_links);
> @@ -1009,9 +986,6 @@ static void mst_stream_disable(struct intel_atomic_state
> *state,
> intel_hdcp_disable(intel_mst->connector);
>
> intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
> -
> - if (DISPLAY_VER(display) >= 20)
> - intel_de_write(display, DP_MIN_HBLANK_CTL(trans), 0);
> }
>
> static void mst_stream_post_disable(struct intel_atomic_state *state,
> @@ -1286,7 +1260,7 @@ static void mst_stream_enable(struct intel_atomic_state
> *state,
> enum transcoder trans = pipe_config->cpu_transcoder;
> bool first_mst_stream = intel_dp->mst.active_links == 1;
> struct intel_crtc *pipe_crtc;
> - int ret, i, min_hblank;
> + int ret, i;
>
> drm_WARN_ON(display->drm, pipe_config->has_pch_encoder);
>
> @@ -1301,29 +1275,6 @@ static void mst_stream_enable(struct
> intel_atomic_state *state,
> TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz &
> 0xffffff));
> }
>
> - if (DISPLAY_VER(display) >= 20) {
> - /*
> - * adjust the BlankingStart/BlankingEnd framing control from
> - * the calculated value
> - */
> - min_hblank = pipe_config->min_hblank - 2;
> -
> - /* Maximum value to be programmed is limited to 0x10 */
> - min_hblank = min(0x10, min_hblank);
> -
> - /*
> - * Minimum hblank accepted for 128b/132b would be 5 and for
> - * 8b/10b would be 3 symbol count
> - */
> - if (intel_dp_is_uhbr(pipe_config))
> - min_hblank = max(min_hblank, 5);
> - else
> - min_hblank = max(min_hblank, 3);
> -
> - intel_de_write(display, DP_MIN_HBLANK_CTL(trans),
> - min_hblank);
> - }
> -
> enable_bs_jitter_was(pipe_config);
>
> intel_ddi_enable_transcoder_func(encoder, pipe_config);
>
> --
> 2.25.1
>
