On 04/04/2025 09:09, Boris Brezillon wrote:
> MMU handler needs to be in control of the job interrupt clears because
> clearing the interrupt also unblocks the writer/reader that triggered
> the fault, and we don't want it to be unblocked until we've had a chance
> to process the IRQ.
> 
> Since clearing the clearing is just one line, let's make it explicit
> instead of doing it in the generic code path.
> 
> Note that this commit changes the existing behavior in that the MMU
> COMPLETED irqs are no longer cleared, which is fine because they are
> masked, so we're not risking an interrupt flood.
> 
> Changes in v3:
> - Mention the fact we no longer clear MMU COMPLETED irqs

Thanks!

Reviewed-by: Steven Price <steven.pr...@arm.com>

> - Add Liviu's R-b
> 
> Changes in v2:
> - Move the MMU_INT_CLEAR around
> 
> Signed-off-by: Boris Brezillon <boris.brezil...@collabora.com>
> Reviewed-by: Liviu Dudau <liviu.du...@arm.com>
> ---
>  drivers/gpu/drm/panthor/panthor_device.h | 2 --
>  drivers/gpu/drm/panthor/panthor_fw.c     | 2 ++
>  drivers/gpu/drm/panthor/panthor_gpu.c    | 2 ++
>  drivers/gpu/drm/panthor/panthor_mmu.c    | 7 +++++++
>  4 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panthor/panthor_device.h 
> b/drivers/gpu/drm/panthor/panthor_device.h
> index da6574021664..4c27b6d85f46 100644
> --- a/drivers/gpu/drm/panthor/panthor_device.h
> +++ b/drivers/gpu/drm/panthor/panthor_device.h
> @@ -383,8 +383,6 @@ static irqreturn_t panthor_ ## __name ## 
> _irq_threaded_handler(int irq, void *da
>               if (!status)                                                    
>                 \
>                       break;                                                  
>                 \
>                                                                               
>                 \
> -             gpu_write(ptdev, __reg_prefix ## _INT_CLEAR, status);           
>                 \
> -                                                                             
>                 \
>               __handler(ptdev, status);                                       
>                 \
>               ret = IRQ_HANDLED;                                              
>                 \
>       }                                                                       
>                 \
> diff --git a/drivers/gpu/drm/panthor/panthor_fw.c 
> b/drivers/gpu/drm/panthor/panthor_fw.c
> index 0f52766a3120..446bb377b953 100644
> --- a/drivers/gpu/drm/panthor/panthor_fw.c
> +++ b/drivers/gpu/drm/panthor/panthor_fw.c
> @@ -1008,6 +1008,8 @@ static void panthor_fw_init_global_iface(struct 
> panthor_device *ptdev)
>  
>  static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 status)
>  {
> +     gpu_write(ptdev, JOB_INT_CLEAR, status);
> +
>       if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF))
>               ptdev->fw->booted = true;
>  
> diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c 
> b/drivers/gpu/drm/panthor/panthor_gpu.c
> index 671049020afa..32d678a0114e 100644
> --- a/drivers/gpu/drm/panthor/panthor_gpu.c
> +++ b/drivers/gpu/drm/panthor/panthor_gpu.c
> @@ -150,6 +150,8 @@ static void panthor_gpu_init_info(struct panthor_device 
> *ptdev)
>  
>  static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status)
>  {
> +     gpu_write(ptdev, GPU_INT_CLEAR, status);
> +
>       if (status & GPU_IRQ_FAULT) {
>               u32 fault_status = gpu_read(ptdev, GPU_FAULT_STATUS);
>               u64 address = ((u64)gpu_read(ptdev, GPU_FAULT_ADDR_HI) << 32) |
> diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c 
> b/drivers/gpu/drm/panthor/panthor_mmu.c
> index 7cca97d298ea..0ba76982d45b 100644
> --- a/drivers/gpu/drm/panthor/panthor_mmu.c
> +++ b/drivers/gpu/drm/panthor/panthor_mmu.c
> @@ -1710,6 +1710,13 @@ static void panthor_mmu_irq_handler(struct 
> panthor_device *ptdev, u32 status)
>                       access_type, access_type_name(ptdev, fault_status),
>                       source_id);
>  
> +             /* We don't handle VM faults at the moment, so let's just clear 
> the
> +              * interrupt and let the writer/reader crash.
> +              * Note that COMPLETED irqs are never cleared, but this is fine
> +              * because they are always masked.
> +              */
> +             gpu_write(ptdev, MMU_INT_CLEAR, mask);
> +
>               /* Ignore MMU interrupts on this AS until it's been
>                * re-enabled.
>                */

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