When we clear the faulty bits in the AS mask, we also need to update
the panthor_mmu::irq::mask field otherwise our IRQ handler won't get
called again until the GPU is reset.

Changes in v2:
- Add Liviu's R-b

Fixes: 647810ec2476 ("drm/panthor: Add the MMU/VM logical block")
Signed-off-by: Boris Brezillon <boris.brezil...@collabora.com>
Reviewed-by: Liviu Dudau <liviu.du...@arm.com>
---
 drivers/gpu/drm/panthor/panthor_mmu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c 
b/drivers/gpu/drm/panthor/panthor_mmu.c
index 12a02e28f50f..7cca97d298ea 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu.c
+++ b/drivers/gpu/drm/panthor/panthor_mmu.c
@@ -781,6 +781,7 @@ int panthor_vm_active(struct panthor_vm *vm)
        if (ptdev->mmu->as.faulty_mask & panthor_mmu_as_fault_mask(ptdev, as)) {
                gpu_write(ptdev, MMU_INT_CLEAR, 
panthor_mmu_as_fault_mask(ptdev, as));
                ptdev->mmu->as.faulty_mask &= ~panthor_mmu_as_fault_mask(ptdev, 
as);
+               ptdev->mmu->irq.mask |= panthor_mmu_as_fault_mask(ptdev, as);
                gpu_write(ptdev, MMU_INT_MASK, ~ptdev->mmu->as.faulty_mask);
        }
 
-- 
2.49.0

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