If anx7625 interrupt cannot be processed intime, it will cause
race condition. This is the root cause of not display after S4/S5
resume back. The interrupt change status cleared by previously
interrupt action.
Eg: the first interrupt reported at time A, but interrupt postponed
to time B process, at this moment, received 2nd interrupt. It will
cause 1st interrupt clear operation clear 2nd interrupt status.
Remove clear interrupt change status to avoid interrupt change status
missed issue.
Note:
The interrupt change registers of anx7625 doesn't support write clear,
so we can't clear it after read. Otherwise there could be race
conditions between read and clear.
The implementation of the OCM (aka on-chip microprocessor) ensures that
only the first interrupt after power on can be triggered without HPD
change, so we can safely remove the register clear step but keeping
the HPD_STATUS_CHANGE check.
Signed-off-by: Xin Ji <x...@analogixsemi.com>
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c
b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 0b61e77c0398..1afa65756bd2 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -1585,14 +1585,6 @@ static int anx7625_hpd_change_detect(struct anx7625_data
*ctx)
return intr_vector;
}
DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector);
- status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
- INTERFACE_CHANGE_INT,
- intr_vector & (~intr_vector));
- if (status < 0) {
- DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n");
- return status;
- }
-
if (!(intr_vector & HPD_STATUS_CHANGE))
return -ENOENT;
--
2.25.1
