From: Andy Yan <andy....@rock-chips.com>

The RK3036 HDMI DDC bus requires it's PHY's reference clock to be
enabled first before normal DDC communication can be carried out.

Signed-off-by: Andy Yan <andy....@rock-chips.com>
---

 arch/arm/boot/dts/rockchip/rk3036.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi 
b/arch/arm/boot/dts/rockchip/rk3036.dtsi
index 6039a0908af1c..22685cd23a708 100644
--- a/arch/arm/boot/dts/rockchip/rk3036.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi
@@ -403,8 +403,8 @@ hdmi: hdmi@20034000 {
                compatible = "rockchip,rk3036-inno-hdmi";
                reg = <0x20034000 0x4000>;
                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru  PCLK_HDMI>;
-               clock-names = "pclk";
+               clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>;
+               clock-names = "pclk", "ref";
                pinctrl-names = "default";
                pinctrl-0 = <&hdmi_ctl>;
                #sound-dai-cells = <0>;
-- 
2.43.0

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