On Fri, Mar 21, 2025 at 11:54:37AM -0700, Rob Clark wrote: > From: Rob Clark <robdcl...@chromium.org> > > Really the only purpose of this was to limit the address space size to > 4GB to avoid 32b rollover problems in 64b pointer math in older sqe fw. > So replace the address_space_size with a quirk limiting the address > space to 4GB. In all other cases, use the SMMU input address size (IAS) > to determine the address space size. > > Signed-off-by: Rob Clark <robdcl...@chromium.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 33 +++++++++++------------ > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++++--- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- > 3 files changed, 33 insertions(+), 21 deletions(-) >
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@oss.qualcomm.com> -- With best wishes Dmitry
