The instance of the GPU populated in Freescale i.MX95 does require
release from reset by writing into a single GPUMIX block controller
GPURESET register bit 0. Document support for this reset register.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: Boris Brezillon <boris.brezil...@collabora.com>
Cc: Conor Dooley <conor...@kernel.org>
Cc: David Airlie <airl...@gmail.com>
Cc: Fabio Estevam <feste...@gmail.com>
Cc: Krzysztof Kozlowski <krzk...@kernel.org>
Cc: Liviu Dudau <liviu.du...@arm.com>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Maxime Ripard <mrip...@kernel.org>
Cc: Pengutronix Kernel Team <ker...@pengutronix.de>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Cc: Rob Herring <r...@kernel.org>
Cc: Sascha Hauer <s.ha...@pengutronix.de>
Cc: Sebastian Reichel <s...@kernel.org>
Cc: Shawn Guo <shawn...@kernel.org>
Cc: Simona Vetter <sim...@ffwll.ch>
Cc: Steven Price <steven.pr...@arm.com>
Cc: Thomas Zimmermann <tzimmerm...@suse.de>
Cc: devicet...@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: i...@lists.linux.dev
Cc: linux-arm-ker...@lists.infradead.org
---
V2: - Fix dt_binding_check errors in example, temporarily use fixed
numbers to refer to IMX95_CLK_GPUAPB clock and IMX95_PD_GPU
power-domain
- Drop trailing pipe after description:
- Drop leading dash before const in compatible:
- Switch from fsl, to nxp, vendor prefix
---
.../reset/nxp,imx95-gpu-blk-ctrl.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/nxp,imx95-gpu-blk-ctrl.yaml
diff --git
a/Documentation/devicetree/bindings/reset/nxp,imx95-gpu-blk-ctrl.yaml
b/Documentation/devicetree/bindings/reset/nxp,imx95-gpu-blk-ctrl.yaml
new file mode 100644
index 0000000000000..ca841db20d35b
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/nxp,imx95-gpu-blk-ctrl.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/nxp,imx95-gpu-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX95 GPU Block Controller
+
+maintainers:
+ - Marek Vasut <ma...@denx.de>
+
+description:
+ This reset controller is a block of ad-hoc debug registers, one of
+ which is a single-bit GPU reset.
+
+properties:
+ compatible:
+ const: nxp,imx95-gpu-blk-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@4d810000 {
+ compatible = "nxp,imx95-gpu-blk-ctrl";
+ reg = <0x4d810000 0xc>;
+ clocks = <&clk 83>;
+ power-domains = <&scmi_devpd 14>;
+ #reset-cells = <1>;
+ };
--
2.47.2
