The instance of the GPU populated in i.MX95 is the G310,
describe this GPU in the DT. Include description of the
GPUMIX block controller, which can be operated as a simple
reset. Include dummy GPU voltage regulator and OPP tables.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: Boris Brezillon <boris.brezil...@collabora.com>
Cc: Conor Dooley <conor...@kernel.org>
Cc: David Airlie <airl...@gmail.com>
Cc: Fabio Estevam <feste...@gmail.com>
Cc: Krzysztof Kozlowski <krzk...@kernel.org>
Cc: Liviu Dudau <liviu.du...@arm.com>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Maxime Ripard <mrip...@kernel.org>
Cc: Pengutronix Kernel Team <ker...@pengutronix.de>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Cc: Rob Herring <r...@kernel.org>
Cc: Sascha Hauer <s.ha...@pengutronix.de>
Cc: Sebastian Reichel <s...@kernel.org>
Cc: Shawn Guo <shawn...@kernel.org>
Cc: Simona Vetter <sim...@ffwll.ch>
Cc: Steven Price <steven.pr...@arm.com>
Cc: Thomas Zimmermann <tzimmerm...@suse.de>
Cc: devicet...@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: i...@lists.linux.dev
Cc: linux-arm-ker...@lists.infradead.org
---
V2: - Drop regulator-{always,boot}-on from fixed-gpu-reg regulator
- Keep the GPU and GPUMIX always enabled
- Switch from fsl, to nxp, vendor prefix
- Fix opp_table to opp-table
- Describe IMX95_CLK_GPUAPB as coregroup clock
- Sort interrupts by their names to match bindings
---
arch/arm64/boot/dts/freescale/imx95.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi
b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 9bb26b466a061..3acdbd7fd4eee 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -249,6 +249,35 @@ dummy: clock-dummy {
clock-output-names = "dummy";
};
+ gpu_fixed_reg: fixed-gpu-reg {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <920000>;
+ regulator-name = "vdd_gpu";
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-hz-real = /bits/ 64 <500000000>;
+ opp-microvolt = <920000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-hz-real = /bits/ 64 <800000000>;
+ opp-microvolt = <920000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-hz-real = /bits/ 64 <1000000000>;
+ opp-microvolt = <920000>;
+ };
+ };
+
clk_ext1: clock-ext1 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -1890,6 +1919,35 @@ netc_emdio: mdio@0,0 {
};
};
+ gpu_blk_ctrl: reset-controller@4d810000 {
+ compatible = "nxp,imx95-gpu-blk-ctrl";
+ reg = <0x0 0x4d810000 0x0 0xc>;
+ #reset-cells = <1>;
+ clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
+ assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
+ assigned-clock-parents = <&scmi_clk
IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <133333333>;
+ power-domains = <&scmi_devpd IMX95_PD_GPU>;
+ };
+
+ gpu: gpu@4d900000 {
+ compatible = "nxp,imx95-mali", "arm,mali-valhall-csf";
+ reg = <0 0x4d900000 0 0x480000>;
+ clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk
IMX95_CLK_GPUAPB>;
+ clock-names = "core", "coregroup";
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ mali-supply = <&gpu_fixed_reg>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf
IMX95_PERF_GPU>;
+ power-domain-names = "mix", "perf";
+ resets = <&gpu_blk_ctrl 0>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <1013>;
+ };
+
ddr-pmu@4e090dc0 {
compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";
reg = <0x0 0x4e090dc0 0x0 0x200>;
--
2.47.2
