On 3/3/25 4:04 PM, Liviu Dudau wrote:
[...]
+ #reset-cells = <1>;
+ clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
+ assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
+ assigned-clock-parents = <&scmi_clk
IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <133333333>;
+ power-domains = <&scmi_devpd IMX95_PD_GPU>;
+ status = "disabled";
+ };
+
+ gpu: gpu@4d900000 {
+ compatible = "fsl,imx95-mali", "arm,mali-valhall-csf";
+ reg = <0 0x4d900000 0 0x480000>;
+ clocks = <&scmi_clk IMX95_CLK_GPU>;
There is also IMX95_CLK_GPUAPB. Is this only required for the rese control
above?
I think I have to describe those clock here too, possibly as 'coregroup'
clock ?
The 'coregroup' clock does indeed control the MMU and L2$ blocks as well as the
AXI interface,
so if that is indeed a separate external clock source it should be defined.
Could it be why
you're seeing issues with L2$ resume on the fast reset path?
Sorry for the delayed reply.
I did define these clock, they are enabled, but the L2 reset problem is
still present .
