On 8.03.2025 2:42 AM, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
>
> Qualcomm SAR2130P requires slightly different setup for the DSI PHY. It
> is a 5nm PHY (like SM8450), so supplies are the same, but the rest of
> the configuration is the same as SM8550 DSI PHY.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++
> 3 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index
> c0bcc68289633fd7506ce4f1f963655d862e8f08..a58bafe9fe8635730cb82e8c82ec1ded394988cd
> 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -581,6 +581,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> .data = &dsi_phy_7nm_cfgs },
> { .compatible = "qcom,dsi-phy-7nm-8150",
> .data = &dsi_phy_7nm_8150_cfgs },
> + { .compatible = "qcom,sar2130p-dsi-phy-5nm",
> + .data = &dsi_phy_5nm_sar2130p_cfgs },
> { .compatible = "qcom,sc7280-dsi-phy-7nm",
> .data = &dsi_phy_7nm_7280_cfgs },
> { .compatible = "qcom,sm6375-dsi-phy-7nm",
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index
> 1925418d9999a24263d6621299cae78f1fb9455c..1ed08b56e056094bc0096d07d4470b89d9824060
> 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index
> a92decbee5b5433853ed973747f7705d9079068d..cad55702746b8d35949d22090796cca60f03b9e1
> 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -1289,6 +1289,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
> .quirks = DSI_PHY_7NM_QUIRK_V4_3,
> };
>
> +const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs = {
> + .has_phy_lane = true,
> + .regulator_data = dsi_phy_7nm_97800uA_regulators,
> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators),
> + .ops = {
> + .enable = dsi_7nm_phy_enable,
> + .disable = dsi_7nm_phy_disable,
> + .pll_init = dsi_pll_7nm_init,
> + .save_pll_state = dsi_7nm_pll_save_state,
> + .restore_pll_state = dsi_7nm_pll_restore_state,
> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
> + },
> + .min_pll_rate = 600000000UL,
> +#ifdef CONFIG_64BIT
> + .max_pll_rate = 5000000000UL,
> +#else
> + .max_pll_rate = ULONG_MAX,
> +#endif
> + .io_start = { 0xae95000, 0xae97000 },
> + .num_dsi_phy = 2,
> + .quirks = DSI_PHY_7NM_QUIRK_V5_2,
> +};
I'm squinting very very hard and can't tell how this is different from
dsi_phy_4nm_8550_cfgs
Konrad
