On 2/13/2025 10:51 PM, Konrad Dybcio wrote:
> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
>> From: Jie Zhang <quic_ji...@quicinc.com>
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang <quic_ji...@quicinc.com>
>> Signed-off-by: Akhil P Oommen <quic_akhi...@quicinc.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29
>> +++++++++++++++++++++++++++++
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++
>> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +-
>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++
>> 4 files changed, 43 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index edffb7737a97..ac156c8b5af9 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -879,6 +879,35 @@ static const struct adreno_info a6xx_gpus[] = {
>> { 0, 0 },
>> { 137, 1 },
>> ),
>> + }, {
>> + .chip_ids = ADRENO_CHIP_IDS(0x06020300),
>> + .family = ADRENO_6XX_GEN3,
>> + .fw = {
>> + [ADRENO_FW_SQE] = "a650_sqe.fw",
>> + [ADRENO_FW_GMU] = "a623_gmu.bin",
>> + },
>> + .gmem = SZ_512K,
>> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
>> + ADRENO_QUIRK_HAS_HW_APRIV,
>> + .init = a6xx_gpu_init,
>> + .a6xx = &(const struct a6xx_info) {
>> + .hwcg = a620_hwcg,
>
> On downstream a663 hwcg table is used, with the following differences:
>
> < A620
>> A663
>
> < {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
>> {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
>
> < {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
>> {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}
Thanks. We ended up reviewing this with HW folks and found that the
downstream code is incorrect too. Will send another revision.
-Akhil.
>
> Konrad
